Architecture >> I2cMaster::rtl

Processes
comb	( byteCtrlOut , i2cMasterIn , r , srst )
reg	( arst , clk )
comb	( byteCtrlOut , i2cMasterIn , r , srst )
reg	( arst , clk )

Constants
TIMEOUT_C	*integer := ( PRESCALE_G+ 1 ) 5 * 500**
REG_INIT_C	RegType := ( timer = > 0 , coreRst = > ' 0 ' , byteCtrlIn = > ( start = > ' 0 ' , stop = > ' 0 ' , read = > ' 0 ' , write = > ' 0 ' , ackIn = > ' 0 ' , din = > ( others = > ' 0 ' ) ) , state = > WAIT_TXN_REQ_S , tenbit = > ' 0 ' , i2cMasterOut = > ( busAck = > ' 0 ' , txnError = > ' 0 ' , wrAck = > ' 0 ' , rdValid = > ' 0 ' , rdData = > ( others = > ' 0 ' ) ) )

Types
StateType	( WAIT_TXN_REQ_S , ADDR_S , WAIT_ADDR_ACK_S , READ_S , WAIT_READ_DATA_S , WRITE_S , WAIT_WRITE_ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
byteCtrlOut	ByteCtrlOutType
iSclOEn	sl
iSdaOEn	sl
filter	*slv ( ( FILTER_G- 1 ) DYNAMIC_FILTER_G downto 0 )**
arstL	sl
coreRst	sl

Instantiations
byte_ctrl	i2c_master_byte_ctrl <Entity i2c_master_byte_ctrl>
byte_ctrl	i2c_master_byte_ctrl <Entity i2c_master_byte_ctrl>

The documentation for this design unit was generated from the following files:

Processes

Constants