Heartbeat Entity Reference

Inheritance diagram for Heartbeat:

Entities
Heartbeat.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
USE_DSP_G	string := " no "
PERIOD_IN_G	real := 6 . 4E - 9
PERIOD_OUT_G	real := 1 . 0E - 0

Ports
clk	in	sl
rst	in	sl := ' 0 '
o	out	sl

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The documentation for this design unit was generated from the following files:

• base/general/rtl/Heartbeat.vhd
• build/SRC_VHDL/surf/Heartbeat.vhd