Gtx7RecClkMonitor.RTL Architecture Reference

Architecture >> Gtx7RecClkMonitor::RTL

Functions
boolean	simulation_func

Processes
PROCESS_431	( RX_REC_CLK0 )
PROCESS_432	( RX_REC_CLK0 )
PROCESS_433	( REF_CLK )
PROCESS_434	( REF_CLK )
PROCESS_435	( SYSTEM_CLK )
PROCESS_436	( SYSTEM_CLK )
PROCESS_437	( SYSTEM_CLK )
PROCESS_438	( SYSTEM_CLK )
PROCESS_439	( SYSTEM_CLK )
PROCESS_440	( SYSTEM_CLK )
PROCESS_441	( SYSTEM_CLK )

Constants
simulation	boolean := simulation_func

Types
StateType	( WAIT_FOR_LOCK , REFCLK_EVENT , CALC_PPM_DIFF , CHECK_SIGN , COMP_CNTR , RESTART )

Signals
state	StateType
ref_clk_cnt	std_logic_vector ( COUNTER_UPPER_VALUE- 1 downto 0 )
rec_clk0_cnt	std_logic_vector ( COUNTER_UPPER_VALUE- 1 downto 0 ) := ( others = > ' 0 ' )
rec_clk0_msb	std_logic_vector ( 2 downto 1 )
ref_clk_msb	std_logic_vector ( 2 downto 1 )
rec_clk_0_msb_meta	std_logic
ref_clk_msb_meta	std_logic
sys_clk_counter	std_logic_vector ( GCLK_COUNTER_UPPER_VALUE- 1 downto 0 )
rec_clk0_compare_cnt_latch	std_logic_vector ( GCLK_COUNTER_UPPER_VALUE- 1 downto 0 )
ref_clk_compare_cnt_latch	std_logic_vector ( GCLK_COUNTER_UPPER_VALUE- 1 downto 0 )
g_clk_rst_meta	std_logic
g_clk_rst_sync	std_logic
gt_pll_locked_meta	std_logic
gt_pll_locked_sync	std_logic
reset_logic_rec0_meta	std_logic
reset_logic_rec0_sync	std_logic
reset_logic_ref_meta	std_logic
reset_logic_ref_sync	std_logic
rec_clk0_edge_event	std_logic
ref_clk_edge_event	std_logic_vector ( 1 downto 0 )
ppm0	std_logic_vector ( GCLK_COUNTER_UPPER_VALUE- 1 downto 0 )
recclk_stable0	std_logic
reset_logic	std_logic_vector ( 3 downto 0 )
ref_clk_edge_rt	std_logic_vector ( 1 downto 0 )
g_clk_rst	std_logic
gt_pll_locked	std_logic
rec_clk0_edge	std_logic
ref_clk_edge	std_logic
recclk_stable0_int	std_logic := ' 0 '

Attributes
syn_keep	boolean
syn_keep	signal is true

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtx7/rtl/Gtx7RecClkMonitor.vhd