Gtpe2ChannelDummy Entity Reference

Inheritance diagram for Gtpe2ChannelDummy:

Collaboration diagram for Gtpe2ChannelDummy:

Entities
Gtpe2ChannelDummy.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
EXT_QPLL_G	boolean := false
WIDTH_G	positive range 1 to 4 := 1

Ports
refClk	in	sl
qPllOutClkExt	in	slv ( 1 downto 0 ) := " 00 "
qPllOutRefClkExt	in	slv ( 1 downto 0 ) := " 00 "
gtRxP	in	slv ( WIDTH_G- 1 downto 0 )
gtRxN	in	slv ( WIDTH_G- 1 downto 0 )
gtTxP	out	slv ( WIDTH_G- 1 downto 0 )
gtTxN	out	slv ( WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• xilinx/7Series/gtp7/rtl/Gtpe2ChannelDummy.vhd