GtpTxPhaseAligner Entity Reference

Inheritance diagram for GtpTxPhaseAligner:

Entities
GtpTxPhaseAligner.rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
TPD_G	time := 1 ns

Ports
gtpTxUsrClk2	in	std_logic
gtpReset	in	std_logic
gtpPllLockDetect	in	std_logic
gtpTxEnPmaPhaseAlign	out	std_logic
gtpTxPmaSetPhase	out	std_logic
gtpTxAligned	out	std_logic

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The documentation for this design unit was generated from the following file:

• xilinx/Virtex5/gtp/rtl/GtpTxPhaseAligner.vhd