GtpDualFixedLatCore Entity Reference

Inheritance diagram for GtpDualFixedLatCore:

Collaboration diagram for GtpDualFixedLatCore:

Entities
GtpDualFixedLatCore.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIM_PLL_PERDIV2	bit_vector := X " 0C8 "
CLK25_DIVIDER	integer := 5
PLL_DIVSEL_FB	integer := 2
PLL_DIVSEL_REF	integer := 1
REC_CLK_PERIOD	real := 4 . 000
REC_PLL_MULT	integer := 4
REC_PLL_DIV	integer := 1

Ports
gtpClkIn	in	std_logic
gtpRefClkOut	out	std_logic
gtpRxN	in	slv ( 1 downto 0 )
gtpRxP	in	slv ( 1 downto 0 )
gtpTxN	out	slv ( 1 downto 0 )
gtpTxP	out	slv ( 1 downto 0 )
gtpReset	in	std_logic
gtpResetDone	out	slv ( 1 downto 0 )
gtpPllLockDet	out	std_logic
gtpLoopback	in	slv ( 1 downto 0 )
gtpRxReset	in	slv ( 1 downto 0 )
gtpRxCdrReset	in	slv ( 1 downto 0 )
gtpRxElecIdle	out	slv ( 1 downto 0 )
gtpRxElecIdleRst	in	slv ( 1 downto 0 )
gtpRxUsrClk	out	slv ( 1 downto 0 )
gtpRxUsrClk2	out	slv ( 1 downto 0 )
gtpRxUsrClkRst	out	slv ( 1 downto 0 )
gtpRxData	out	slv16Array ( 1 downto 0 )
gtpRxDataK	out	slv2Array ( 1 downto 0 )
gtpRxDecErr	out	slv2Array ( 1 downto 0 )
gtpRxDispErr	out	slv2Array ( 1 downto 0 )
gtpRxPolarity	in	slv ( 1 downto 0 )
gtpRxAligned	out	slv ( 1 downto 0 )
gtpTxReset	in	slv ( 1 downto 0 )
gtpTxUsrClk	in	std_logic
gtpTxUsrClk2	in	std_logic
gtpTxAligned	out	std_logic
gtpTxData	in	slv16Array ( 1 downto 0 )
gtpTxDataK	in	slv2Array ( 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• xilinx/Virtex5/gtp/rtl/GtpDualFixedLatCore.vhd