Gearbox.rtl Architecture Reference

Architecture >> Gearbox::rtl

Processes
comb	( masterBitOrder , masterReady , r , rst , slaveBitOrder , slaveData , slaveValid , slip , startOfSeq )
seq	( clk , rst )
comb	( masterBitOrder , masterReady , r , rst , slaveBitOrder , slaveData , slaveValid , slip , startOfSeq )
seq	( clk , rst )

Constants
MAX_C	positive := maximum ( MASTER_WIDTH_G , SLAVE_WIDTH_G )
MIN_C	positive := minimum ( MASTER_WIDTH_G , SLAVE_WIDTH_G )
SHIFT_WIDTH_C	positive := wordCount ( MAX_C , MIN_C ) * MIN_C+ MIN_C+ 1
REG_INIT_C	RegType := ( masterValid = > ' 0 ' , shiftReg = > ( others = > ' 0 ' ) , writeIndex = > 0 , slipArmed = > ' 0 ' , slaveReady = > ' 0 ' , slip = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/general/rtl/Gearbox.vhd
• build/SRC_VHDL/surf/Gearbox.vhd