FIFO2.rtl Architecture Reference

Architecture >> FIFO2::rtl

Processes
PROCESS_118	( CLK )
PROCESS_119	( CLK )

Signals
fullReg	sl
emptyReg	sl
data0Reg	slv ( WIDTH_G- 1 downto 0 )
data1Reg	slv ( WIDTH_G- 1 downto 0 )
d0di	sl
d0d1	sl
d0h	sl
d1di	sl
d0diMask	slv ( WIDTH_G- 1 downto 0 )
d0d1Mask	slv ( WIDTH_G- 1 downto 0 )
d0hMask	slv ( WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/blue-lib/FIFO2.vhd