EthMacTxExportGmii.rtl Architecture Reference

Architecture >> EthMacTxExportGmii::rtl

Processes
comb	( crcOut , ethClkEn , ethRst , macMaster , phyReady , r )
seq	( ethClk )

Constants
AXI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > INT_EMAC_AXIS_CONFIG_C.TSTRB_EN_C , TDATA_BYTES_C = > 1 , TDEST_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TDEST_BITS_C , TID_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TID_BITS_C , TKEEP_MODE_C = > INT_EMAC_AXIS_CONFIG_C.TKEEP_MODE_C , TUSER_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TUSER_BITS_C , TUSER_MODE_C = > INT_EMAC_AXIS_CONFIG_C.TUSER_MODE_C )
REG_INIT_C	RegType := ( gmiiTxEn = > ' 0 ' , gmiiTxEr = > ' 0 ' , gmiiTxd = > ( others = > ' 0 ' ) , txCount = > ( others = > ' 0 ' ) , txData = > ( others = > ' 0 ' ) , txCountEn = > ' 0 ' , txUnderRun = > ' 0 ' , txLinkNotReady = > ' 0 ' , crcReset = > ' 0 ' , crcDataValid = > ' 0 ' , crcIn = > ( others = > ' 0 ' ) , state = > IDLE_S , macSlave = > AXI_STREAM_SLAVE_INIT_C )

Types
StateType	( IDLE_S , TX_PREAMBLE_S , TX_DATA_S , PAD_S , TX_CRC_S , TX_CRC0_S , TX_CRC1_S , TX_CRC2_S , TX_CRC3_S , DUMP_S , INTERGAP_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
macMaster	AxiStreamMasterType
macSlave	AxiStreamSlaveType
crcOut	slv ( 31 downto 0 )
crcDataValid	sl
crcIn	slv ( 7 downto 0 )

Records
RegType

Instantiations
u_resize	AxiStreamResize <Entity AxiStreamResize>
u_crc32	Crc32Parallel <Entity Crc32Parallel>

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthMacTxExportGmii.vhd