EthMacTxBypass.rtl Architecture Reference

Architecture >> EthMacTxBypass::rtl

Processes
comb	( ethRst , mAxisSlave , r , sBypMaster , sPrimMaster )
seq	( ethClk )

Constants
REG_INIT_C	RegType := ( mAxisMaster = > AXI_STREAM_MASTER_INIT_C , sPrimSlave = > AXI_STREAM_SLAVE_INIT_C , sBypSlave = > AXI_STREAM_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , PRIM_S , BYP_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthMacTxBypass.vhd