EthMacRxImportXgmii.rtl Architecture Reference

Architecture >> EthMacRxImportXgmii::rtl

Processes
comb	( phyRxChar , phyRxdata , r )
seq	( ethClk )
PROCESS_219	( ethClk )
PROCESS_220	( crcDataValid , crcDataWidth , phyRxc , phyRxcDly , rxdAlign )
PROCESS_221	( ethClk )
PROCESS_222	( ethClk )

Constants
AXI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > INT_EMAC_AXIS_CONFIG_C.TSTRB_EN_C , TDATA_BYTES_C = > 8 , TDEST_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TDEST_BITS_C , TID_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TID_BITS_C , TKEEP_MODE_C = > INT_EMAC_AXIS_CONFIG_C.TKEEP_MODE_C , TUSER_BITS_C = > INT_EMAC_AXIS_CONFIG_C.TUSER_BITS_C , TUSER_MODE_C = > INT_EMAC_AXIS_CONFIG_C.TUSER_MODE_C )
REG_INIT_C	RegType := ( phyRxd = > x " 0707070707070707 " , phyRxc = > x " FF " , phyRxdDly = > x " 0707070707070707 " , phyRxcDly = > x " FF " , gapInserted = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
macMaster	AxiStreamMasterType
frameShift0	sl
frameShift1	sl
frameShift2	sl
frameShift3	sl
frameShift4	sl
frameShift5	sl
rxdAlign	sl
dlyRxd	slv ( 31 downto 0 )
crcDataWidth	slv ( 2 downto 0 )
nxtCrcWidth	slv ( 2 downto 0 )
nxtCrcValid	sl
crcDataValid	sl
crcFifoIn	slv ( 63 downto 0 )
crcFifoOut	slv ( 63 downto 0 )
phyRxcDly	slv ( 7 downto 0 )
crcWidthDly0	slv ( 2 downto 0 )
crcWidthDly1	slv ( 2 downto 0 )
crcWidthDly2	slv ( 2 downto 0 )
crcWidthDly3	slv ( 2 downto 0 )
crcShift0	sl
crcShift1	sl
endDetect	sl
endShift0	sl
endShift1	sl
crcGood	sl
intLastLine	sl
intFirstLine	sl
intAdvance	sl
lastSOF	sl
crcIn	slv ( 63 downto 0 )
crcInit	sl
crcReset	sl
crcOut	slv ( 31 downto 0 )
macData	slv ( 63 downto 0 )
macSize	slv ( 2 downto 0 )
phyRxd	slv ( 63 downto 0 )
phyRxc	slv ( 7 downto 0 )

Attributes
dont_touch	string
dont_touch	signal is " true "

Records
RegType

Instantiations
u_resize	AxiStreamResize <Entity AxiStreamResize>
u_crcfifo	Fifo <Entity Fifo>
u_crc32	Crc32Parallel <Entity Crc32Parallel>

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthMacRxImportXgmii.vhd