EthMacRxCheckICrc.rtl Architecture Reference

Architecture >> EthMacRxCheckICrc::rtl

Processes
comb	( ethRst , mAxisSlave , r , sAxisCrcCheckMaster , sAxisMaster )
seq	( ethClk , ethRst )

Constants
REG_INIT_C	RegType := ( gotCrc = > ' 0 ' , ibSlave = > AXI_STREAM_SLAVE_INIT_C , ibCrcSlave = > AXI_STREAM_SLAVE_INIT_C , obMaster = > axiStreamMasterInit ( EMAC_AXIS_CONFIG_C ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/EthMacRxCheckICrc.vhd