EthMacRxBypass Entity Reference

Inheritance diagram for EthMacRxBypass:

Entities
EthMacRxBypass.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
AxiStreamPkg	Package <AxiStreamPkg>
StdRtlPkg	Package <StdRtlPkg>
EthMacPkg	Package <EthMacPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
BYP_EN_G	boolean := false
BYP_ETH_TYPE_G	slv ( 15 downto 0 ) := x " 0000 "

Ports
ethClk	in	sl
ethRst	in	sl
sAxisMaster	in	AxiStreamMasterType
mPrimMaster	out	AxiStreamMasterType
mBypMaster	out	AxiStreamMasterType

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The documentation for this design unit was generated from the following file:

• ethernet/EthMacCore/rtl/EthMacRxBypass.vhd