EthMacPrepareForICrc.rtl Architecture Reference

Architecture >> EthMacPrepareForICrc::rtl

Processes
comb	( ethRst , mAxisSlave , r , sAxisMaster )
seq	( ethClk )

Constants
REG_INIT_C	RegType := ( cnt = > 0 , obMaster = > AXI_STREAM_MASTER_INIT_C , ibSlave = > AXI_STREAM_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/EthMacPrepareForICrc.vhd