Decoder12b14b.rtl Architecture Reference

Architecture >> Decoder12b14b::rtl

Processes
comb	( dataIn , dispIn , r , rst , validIn )
seq	( clk , rst )
comb	( dataIn , dispIn , r , rst , validIn )
seq	( clk , rst )

Constants
REG_INIT_C	RegType := ( validOut = > ' 0 ' , dispOut = > " 00 " , dataOut = > ( others = > ' 0 ' ) , dataKOut = > ' 0 ' , codeError = > ' 0 ' , dispError = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Decoder12b14b.vhd
• protocols/line-codes/rtl/Decoder12b14b.vhd