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Decoder10b12b Entity Reference
Inheritance diagram for Decoder10b12b:Entities | |
| Decoder10b12b.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| StdRtlPkg | Package <StdRtlPkg> |
| Code10b12bPkg | Package <Code10b12bPkg> |
Generics | |
| TPD_G | time := 1 ns |
| RST_POLARITY_G | sl := ' 0 ' |
| RST_ASYNC_G | boolean := true |
| USE_CLK_EN_G | boolean := false |
Ports | ||
| clk | in | sl |
| clkEn | in | sl := ' 1 ' |
| rst | in | sl := not RST_POLARITY_G |
| validIn | in | sl := ' 1 ' |
| dataIn | in | slv ( 11 downto 0 ) |
| dataOut | out | slv ( 9 downto 0 ) |
| dataKOut | out | sl |
| validOut | out | sl |
| dispOut | out | sl |
| codeError | out | sl |
| dispError | out | sl |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/Decoder10b12b.vhd
- protocols/line-codes/rtl/Decoder10b12b.vhd
