Counter Entity Reference

Inheritance diagram for Counter:

Entities
Counter.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
WIDTH_G	positive := 1
INIT_G	natural := 0

Ports
CLK	in	sl
RST	in	sl
Q_OUT	out	slv ( WIDTH_G- 1 downto 0 )
DATA_A	in	slv ( WIDTH_G- 1 downto 0 )
ADDA	in	sl
DATA_B	in	slv ( WIDTH_G- 1 downto 0 )
ADDB	in	sl
DATA_C	in	slv ( WIDTH_G- 1 downto 0 )
SETC	in	sl
DATA_F	in	slv ( WIDTH_G- 1 downto 0 )
SETF	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/blue-lib/Counter.vhd