Code10b12bTb.sim Architecture Reference

Architecture >> Code10b12bTb::sim

Processes
main
main

Constants
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false

Signals
encDataInString	string ( 1 to 8 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Code10b12bTb.vhd
• protocols/line-codes/tb/Code10b12bTb.vhd