CoaxpressOverFiberGtyUsQpll Entity Reference

Inheritance diagram for CoaxpressOverFiberGtyUsQpll:

Collaboration diagram for CoaxpressOverFiberGtyUsQpll:

Entities
CoaxpressOverFiberGtyUsQpll.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
REF_CLK_FREQ_G	real := 156 . 25E + 6
QPLL_REFCLK_SEL_G	slv ( 2 downto 0 ) := " 001 "

Ports
gtRefClk	in	sl := ' 0 '
gtClkP	in	sl := ' 1 '
gtClkN	in	sl := ' 0 '
coreClk	out	sl
coreRst	in	sl := ' 0 '
gtClk	out	sl
qplllock	out	slv ( 1 downto 0 )
qplloutclk	out	slv ( 1 downto 0 )
qplloutrefclk	out	slv ( 1 downto 0 )
qpllRst	in	slv ( 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/gtyUs+/rtl/CoaxpressOverFiberGtyUsQpll.vhd