CoaXPressRxCorePathWrapper Entity Reference

Inheritance diagram for CoaXPressRxCorePathWrapper:

Collaboration diagram for CoaXPressRxCorePathWrapper:

Entities
CoaXPressRxCorePathWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
NUM_LANES_G	positive range 1 to 8 := 1
RX_FSM_CNT_WIDTH_G	positive range 1 to 24 := 8

Ports
dataClk	in	sl
dataRst	in	sl
cfgClk	in	sl
cfgRst	in	sl
txClk	in	sl
txRst	in	sl
rxClk	in	sl
rxRst	in	sl
rxData	in	slv ( 32 * NUM_LANES_G- 1 downto 0 )
rxDataK	in	slv ( 4 * NUM_LANES_G- 1 downto 0 )
rxLinkUp	in	slv ( NUM_LANES_G- 1 downto 0 )
rxFsmRst	in	sl
rxNumberOfLane	in	slv ( 2 downto 0 )
dataTValid	out	sl
dataTData	out	slv ( 31 downto 0 )
dataTKeep	out	slv ( 3 downto 0 )
dataTLast	out	sl
dataTUser	out	slv ( 0 downto 0 )
dataTReady	in	sl
hdrTValid	out	sl
hdrTData	out	slv ( 31 downto 0 )
hdrTKeep	out	slv ( 3 downto 0 )
hdrTLast	out	sl
hdrTUser	out	slv ( 0 downto 0 )
hdrTReady	in	sl
cfgTValid	out	sl
cfgTData	out	slv ( 63 downto 0 )
cfgTKeep	out	slv ( 7 downto 0 )
cfgTLast	out	sl
eventAck	out	sl
eventTag	out	slv ( 7 downto 0 )
trigAck	out	sl
rxOverflow	out	sl
rxFsmError	out	sl

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/core/wrappers/CoaXPressRxCorePathWrapper.vhd