CfixedPreAddMult.rtl Architecture Reference

Architecture >> CfixedPreAddMult::rtl

Processes
comb	( a , aVld , add , b , bVld , d , dVld , r , y )
seq	( clk )

Constants
DELAY_C	integer := 4 + ite ( REG_IN_G , 1 , 0 ) + ite ( REG_OUT_G , 1 , 0 )
REG_DEPTH_C	integer := 3
AD_W_C	integer := 27
AD_LOW_C	integer := minimum ( a.re ' low , d.re ' low )
AD_HIGH_C	integer := maximum ( a.re ' high , d.re ' high ) + 1
AD_HIGH_CLIP_C	integer := minimum ( AD_W_C+ AD_LOW_C- 1 , AD_HIGH_C )
M_LOW_C	integer := AD_LOW_C+ b.re ' low
M_HIGH_C	integer := AD_HIGH_CLIP_C+ b.re ' high+ 1
P_W_C	integer := 48
P_LOW_C	integer := AD_LOW_C+ b.re ' low
P_HIGH_C	integer := P_W_C+ P_LOW_C- 1
INT_OVERFLOW_STYLE_C	fixed_overflow_style_type := fixed_wrap
INT_ROUNDING_STYLE_C	fixed_round_style_type := fixed_truncate
REG_INIT_C	RegType := ( areg = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , breg = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , dreg = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , adreg = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , add_r = > ' 0 ' , add_rr = > ' 0 ' , vld = > ( others = > ' 0 ' ) , m_rr = > ( others = > ' 0 ' ) , m_ii = > ( others = > ' 0 ' ) , m_ri = > ( others = > ' 0 ' ) , m_ir = > ( others = > ' 0 ' ) , p_rr = > ( others = > ' 0 ' ) , p_ii = > ( others = > ' 0 ' ) , p_ri = > ( others = > ' 0 ' ) , p_ir = > ( others = > ' 0 ' ) , y = > ( others = > ( others = > ' 0 ' ) ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

---

The documentation for this design unit was generated from the following file:

• dsp/xilinx/fixed/CfixedPreAddMult.vhd