AxisToJtagStubTb.AxisToJtagStubTbImpl Architecture Reference

Architecture >> AxisToJtagStubTb::AxisToJtagStubTbImpl

Processes
PROCESS_452
U_TX	( clk )
U_RX	( clk )

Signals
clk	sl := ' 0 '
rst	sl := ' 1 '
mAxisReq	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisRep	AxiStreamMasterType
sAxisReq	AxiStreamSlaveType
sAxisRep	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
run	boolean := true
ini	natural := 0
rxs	natural := 0

Instantiations
u_dut	AxisJtagDebugBridge <Entity AxisJtagDebugBridge>

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/tb/AxisToJtagStubTb.vhd