Architecture >> AxiSy56040Reg::rtl
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comb | ( axiReadMaster , axiRst , axiWriteMaster , r ) |
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seq | ( axiClk ) |
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comb | ( axiReadMaster , axiRst , axiWriteMaster , r ) |
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seq | ( axiClk ) |
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PULSE_WIDTH_C | real := 10 . 0E - 9 |
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PULSE_FREQ_C | real := 1 . 0 / PULSE_WIDTH_C |
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MAX_CNT_C | natural := getTimeRatio ( AXI_CLK_FREQ_G , PULSE_FREQ_C ) |
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REG_INIT_C | RegType := ( sin = > ( others = > ' 0 ' ) , sout = > ( others = > ' 0 ' ) , load = > ' 0 ' , config = > XBAR_DEFAULT_G , cnt = > 0 , index = > 0 , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , state = > SETUP_S ) |
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StateType | ( IDLE_S , SETUP_S , LOAD_S , HOLD_S ) |
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r | RegType := REG_INIT_C |
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rin | RegType |
The documentation for this design unit was generated from the following files:
- build/SRC_VHDL/surf/AxiSy56040Reg.vhd
- devices/Microchip/sy56040/rtl/AxiSy56040Reg.vhd
1.9.8