AxiStreamSplitter.rtl Architecture Reference

Architecture >> AxiStreamSplitter::rtl

Processes
comb	( axisRst , mAxisSlaves , r , sAxisMaster )
seq	( axisClk , axisRst )
comb	( axisRst , mAxisSlaves , r , sAxisMaster )
seq	( axisClk , axisRst )

Constants
SEQ_C	slv ( 15 downto 8 ) := x " 55 "
REG_INIT_C	RegType := ( masters = > ( others = > axiStreamMasterInit ( MASTER_AXI_CONFIG_G ) ) , nready = > ( others = > ' 0 ' ) , tSeq = > ( others = > ' 0 ' ) , first = > ' 1 ' , slave = > AXI_STREAM_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamSplitter.vhd
• build/SRC_VHDL/surf/AxiStreamSplitter.vhd