AxiStreamSelector.AxiStreamSelectorImpl Architecture Reference

Architecture >> AxiStreamSelector::AxiStreamSelectorImpl

Processes
P_COMB	( mIb , r , rdyLoc , sel )
P_SEQ	( clk )

Constants
REG_INIT_C	RegType := ( streamBuf = > AXI_STREAM_MASTER_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
rdyLoc	sl

Records
RegType

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/rtl/AxiStreamSelector.vhd