AxiStreamSelectorTb.AxiStreamSelectorTbImpl Architecture Reference

Architecture >> AxiStreamSelectorTb::AxiStreamSelectorTbImpl

Functions
boolean	xferTx ( idx: in natural range 0 to 1 )	[ impure ]
boolean	xferRx

Processes
P_CLK
P_TST	( clk )

Procedures
	assertNoXfer

Constants
DW_C	positive := 8
TPD_G	time := 0 ns

Types
TestMArray	array ( natural range <> ) of TestMType

Signals
clk	sl := ' 0 '
rst	sl := ' 0 '
run	boolean := true
testVec1	TestMArray ( 0 to 9 ) := ( 0 = > ( ' 0 ' , X " A0 " ) , 1 = > ( ' 1 ' , X " A1 " ) , 2 = > ( ' 1 ' , X " A2 " ) , 3 = > ( ' 0 ' , X " A3 " ) , 4 = > ( ' 1 ' , X " A4 " ) , 5 = > ( ' 1 ' , X " A5 " ) , 6 = > ( ' 1 ' , X " A6 " ) , 7 = > ( ' 0 ' , X " A7 " ) , 8 = > ( ' 0 ' , X " A8 " ) , 9 = > ( ' 0 ' , X " A9 " ) )
testVec2	TestMArray ( 0 to 6 ) := ( 0 = > ( ' 0 ' , X " B0 " ) , 1 = > ( ' 0 ' , X " B1 " ) , 2 = > ( ' 1 ' , X " B2 " ) , 3 = > ( ' 0 ' , X " B3 " ) , 4 = > ( ' 1 ' , X " B4 " ) , 5 = > ( ' 1 ' , X " B5 " ) , 6 = > ( ' 1 ' , X " B6 " ) )
mTx	AxiStreamMasterArray ( 1 downto 0 ) := ( others = > AXI_STREAM_MASTER_INIT_C )
sTx	AxiStreamSlaveArray ( 1 downto 0 )
sRx	AxiStreamSlaveType := AXI_STREAM_SLAVE_INIT_C
mRx	AxiStreamMasterType
sel	sl := ' 0 '
stage	natural := 0
t1d	slv ( DW_C- 1 downto 0 )
t0d	slv ( DW_C- 1 downto 0 )
rd	slv ( DW_C- 1 downto 0 )
t1v	sl := ' 0 '
t0v	sl := ' 0 '
rr	sl := ' 0 '

Records
TestMType
TestSType

Instantiations
u_dut	AxiStreamSelector <Entity AxiStreamSelector>

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The documentation for this design unit was generated from the following file:

• xilinx/xvc-udp/jtag/tb/AxiStreamSelectorTb.vhd