Architecture >> AxiStreamScatterGather::rtl

Processes
ramProc	( axiClk )
comb	( axiRst , axilReadMaster , axilWriteMaster , r , sSsiMaster , txFifoRdData , txFifoValid , txRamRdData )
sync	( axiClk )
ramProc	( axiClk )
comb	( axiRst , axilReadMaster , axilWriteMaster , r , sSsiMaster , txFifoRdData , txFifoValid , txRamRdData )
sync	( axiClk )

Constants
SEQUENCE_LENGTH_C	integer := MASTER_AXIS_CONFIG_G.TDATA_BYTES_C/ SLAVE_AXIS_CONFIG_G.TDATA_BYTES_C
SLAVE_DATA_LENGTH_C	*integer := SLAVE_AXIS_CONFIG_G.TDATA_BYTES_C 8**
MASTER_DATA_LENGTH_C	*integer := MASTER_AXIS_CONFIG_G.TDATA_BYTES_C 8**
RAM_DEPTH_RAW_C	*integer := AXIS_SLAVE_FRAME_SIZE_G SEQUENCE_LENGTH_C* 2**
RAM_ADDR_LENGTH_C	integer := bitSize ( RAM_DEPTH_RAW_C )
RAM_DEPTH_C	integer := 2 RAM_ADDR_LENGTH_C**
REG_INIT_C	RegType := ( rxRamWrEn = > ' 0 ' , rxRamWrData = > ( others = > ' 0 ' ) , rxRamWrAddr = > ( others = > ' 0 ' ) , rxSofAddr = > ( others = > ' 0 ' ) , rxFifoWrEn = > ' 0 ' , rxWordCount = > ( others = > ' 0 ' ) , rxFrameNumber = > ( others = > ' 0 ' ) , rxError = > ' 0 ' , mSsiMaster = > ssiMasterInit ( MASTER_AXIS_CONFIG_G ) , txRamRdAddr = > ( others = > ' 0 ' ) , txRamRdEn = > ' 0 ' , txFifoRdEn = > ' 0 ' , txWordCount = > ( others = > ' 0 ' ) , txFrameNumber = > ( others = > ' 0 ' ) , txSof = > ' 1 ' , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , longWordCount = > ( others = > ' 0 ' ) , badWordCount = > ( others = > ' 0 ' ) , longWords = > ( others = > ' 0 ' ) , badWords = > ( others = > ' 0 ' ) )

Types
RamType	( 0 to RAM_DEPTH_C- 1 ) slv ( SLAVE_DATA_LENGTH_C- 1 downto 0 )

Signals
ram	RamType
txRamRdData	slv ( SLAVE_DATA_LENGTH_C- 1 downto 0 )
txFifoRdData	sl
txFifoValid	sl
r	RegType := REG_INIT_C
rin	RegType
sSsiMaster	SsiMasterType

Records
RegType

The documentation for this design unit was generated from the following files:

Processes

Constants