AxiStreamRepeaterIpIntegrator Entity Reference

Inheritance diagram for AxiStreamRepeaterIpIntegrator:

Collaboration diagram for AxiStreamRepeaterIpIntegrator:

Entities
AxiStreamRepeaterIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
DATA_BYTES_G	positive := 4
TUSER_WIDTH_G	positive range 1 to 8 := 1
INCR_AXIS_ID_G	boolean := false
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 0

Ports
axisClk	in	sl
axisRst	in	sl
S_AXIS_TVALID	in	sl := ' 0 '
S_AXIS_TDATA	in	slv ( DATA_BYTES_G* 8 - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TKEEP	in	slv ( DATA_BYTES_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TLAST	in	sl := ' 0 '
S_AXIS_TDEST	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TID	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TUSER	in	slv ( TUSER_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TREADY	out	sl
M0_AXIS_TVALID	out	sl
M0_AXIS_TDATA	out	slv ( DATA_BYTES_G* 8 - 1 downto 0 )
M0_AXIS_TKEEP	out	slv ( DATA_BYTES_G- 1 downto 0 )
M0_AXIS_TLAST	out	sl
M0_AXIS_TDEST	out	slv ( 7 downto 0 )
M0_AXIS_TID	out	slv ( 7 downto 0 )
M0_AXIS_TUSER	out	slv ( TUSER_WIDTH_G- 1 downto 0 )
M0_AXIS_TREADY	in	sl := ' 0 '
M1_AXIS_TVALID	out	sl
M1_AXIS_TDATA	out	slv ( DATA_BYTES_G* 8 - 1 downto 0 )
M1_AXIS_TKEEP	out	slv ( DATA_BYTES_G- 1 downto 0 )
M1_AXIS_TLAST	out	sl
M1_AXIS_TDEST	out	slv ( 7 downto 0 )
M1_AXIS_TID	out	slv ( 7 downto 0 )
M1_AXIS_TUSER	out	slv ( TUSER_WIDTH_G- 1 downto 0 )
M1_AXIS_TREADY	in	sl := ' 0 '

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamRepeaterIpIntegrator.vhd