AxiStreamPipelineIpIntegrator Entity Reference

Inheritance diagram for AxiStreamPipelineIpIntegrator:

Collaboration diagram for AxiStreamPipelineIpIntegrator:

Entities
AxiStreamPipelineIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
DATA_BYTES_G	positive := 4
SIDE_BAND_WIDTH_G	positive := 1
PIPE_STAGES_G	natural := 0

Ports
axisClk	in	sl
axisRst	in	sl
S_AXIS_TVALID	in	sl
S_AXIS_TDATA	in	slv ( DATA_BYTES_G* 8 - 1 downto 0 )
S_AXIS_TKEEP	in	slv ( DATA_BYTES_G- 1 downto 0 )
S_AXIS_TLAST	in	sl
S_AXIS_TDEST	in	slv ( 7 downto 0 )
S_AXIS_TID	in	slv ( 7 downto 0 )
S_AXIS_TREADY	out	sl
S_SIDE_BAND	in	slv ( SIDE_BAND_WIDTH_G- 1 downto 0 )
M_AXIS_TVALID	out	sl
M_AXIS_TDATA	out	slv ( DATA_BYTES_G* 8 - 1 downto 0 )
M_AXIS_TKEEP	out	slv ( DATA_BYTES_G- 1 downto 0 )
M_AXIS_TLAST	out	sl
M_AXIS_TDEST	out	slv ( 7 downto 0 )
M_AXIS_TID	out	slv ( 7 downto 0 )
M_AXIS_TREADY	in	sl
M_SIDE_BAND	out	slv ( SIDE_BAND_WIDTH_G- 1 downto 0 )

---

The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamPipelineIpIntegrator.vhd