Architecture >> AxiStreamGearboxPack::rtl
|
comb | ( axisRst , r , rawSsiMaster ) |
seq | ( axisClk , axisRst ) |
comb | ( axisRst , r , rawSsiMaster ) |
seq | ( axisClk , axisRst ) |
|
STREAM_WIDTH_C | integer := AXI_STREAM_CONFIG_G.TDATA_BYTES_C* 8 |
PACK_SIZE_C | integer := RANGE_HIGH_G- RANGE_LOW_G+ 1 |
SIZE_DIFFERENCE_C | integer := STREAM_WIDTH_C- PACK_SIZE_C |
ASSIGNMENT_INDECIES_C | IntegerArray := computeIndices |
REG_INIT_C | RegType := ( packedSsiMaster = > ssiMasterInit ( AXI_STREAM_CONFIG_G ) , rawSsiSlave = > ssiSlaveInit ( AXI_STREAM_CONFIG_G ) , data = > ( others = > ' 0 ' ) , index = > ( others = > ' 0 ' ) ) |
The documentation for this design unit was generated from the following files:
- axi/axi-stream/rtl/AxiStreamGearboxPack.vhd
- build/SRC_VHDL/surf/AxiStreamGearboxPack.vhd