AxiStreamGearboxIpIntegrator Entity Reference

Inheritance diagram for AxiStreamGearboxIpIntegrator:

Collaboration diagram for AxiStreamGearboxIpIntegrator:

Entities
AxiStreamGearboxIpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
BYTE_PACKER_MODE	natural range 0 to 1 := 0
S_INTERFACENAME	string := " S_AXIS "
S_HAS_TLAST	natural range 0 to 1 := 1
S_HAS_TKEEP	natural range 0 to 1 := 1
S_HAS_TSTRB	natural range 0 to 1 := 0
S_HAS_TREADY	natural range 0 to 1 := 1
S_TUSER_WIDTH	natural range 1 to 8 := 2
S_TID_WIDTH	natural range 1 to 8 := 1
S_TDEST_WIDTH	natural range 1 to 8 := 1
S_TDATA_NUM_BYTES	natural range 1 to 128 := 1
M_INTERFACENAME	string := " M_AXIS "
M_HAS_TLAST	natural range 0 to 1 := 1
M_HAS_TKEEP	natural range 0 to 1 := 1
M_HAS_TSTRB	natural range 0 to 1 := 0
M_HAS_TREADY	natural range 0 to 1 := 1
M_TUSER_WIDTH	natural range 1 to 8 := 2
M_TID_WIDTH	natural range 1 to 8 := 1
M_TDEST_WIDTH	natural range 1 to 8 := 1
M_TDATA_NUM_BYTES	natural range 1 to 128 := 1

Ports
AXIS_ACLK	in	std_logic := ' 0 '
AXIS_ARESETN	in	std_logic := ' 0 '
S_AXIS_TVALID	in	std_logic := ' 0 '
S_AXIS_TDATA	in	std_logic_vector ( ( 8 * S_TDATA_NUM_BYTES ) - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TSTRB	in	std_logic_vector ( S_TDATA_NUM_BYTES- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TKEEP	in	std_logic_vector ( S_TDATA_NUM_BYTES- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TLAST	in	std_logic := ' 0 '
S_AXIS_TDEST	in	std_logic_vector ( S_TDEST_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TID	in	std_logic_vector ( S_TID_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TUSER	in	std_logic_vector ( S_TUSER_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TREADY	out	std_logic
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( ( 8 * M_TDATA_NUM_BYTES ) - 1 downto 0 )
M_AXIS_TSTRB	out	std_logic_vector ( M_TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( M_TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TDEST	out	std_logic_vector ( M_TDEST_WIDTH- 1 downto 0 )
M_AXIS_TID	out	std_logic_vector ( M_TID_WIDTH- 1 downto 0 )
M_AXIS_TUSER	out	std_logic_vector ( M_TUSER_WIDTH- 1 downto 0 )
M_AXIS_TREADY	in	std_logic := ' 1 '

---

The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/AxiStreamGearboxIpIntegrator.vhd