AxiStreamDmaV2ReadIpIntegrator Entity Reference

Inheritance diagram for AxiStreamDmaV2ReadIpIntegrator:

Collaboration diagram for AxiStreamDmaV2ReadIpIntegrator:

Entities
AxiStreamDmaV2ReadIpIntegrator.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
AXIS_READY_EN_G	boolean := false
PIPE_STAGES_G	natural := 1
BURST_BYTES_G	positive range 1 to 4096 := 16
PEND_THRESH_G	positive := 1
DATA_BYTES_G	positive := 4

Ports
axiClk	in	sl
axiRst	in	sl
dmaRdDescReqValid	in	sl := ' 0 '
dmaRdDescReqAddress	in	slv ( 63 downto 0 ) := ( others = > ' 0 ' )
dmaRdDescReqBuffId	in	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
dmaRdDescReqFirstUser	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
dmaRdDescReqLastUser	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
dmaRdDescReqSize	in	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
dmaRdDescReqContinue	in	sl := ' 0 '
dmaRdDescReqId	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
dmaRdDescReqDest	in	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
dmaRdDescAck	out	sl
dmaRdDescRetValid	out	sl
dmaRdDescRetBuffId	out	slv ( 31 downto 0 )
dmaRdDescRetResult	out	slv ( 2 downto 0 )
dmaRdDescRetAck	in	sl := ' 0 '
dmaRdIdle	out	sl
axiCache	in	slv ( 3 downto 0 ) := ( others = > ' 0 ' )
axisCtrlPause	in	sl := ' 0 '
axisCtrlOverflow	in	sl := ' 0 '
M_AXIS_TVALID	out	sl
M_AXIS_TDATA	out	slv ( DATA_BYTES_G* 8 - 1 downto 0 )
M_AXIS_TKEEP	out	slv ( DATA_BYTES_G- 1 downto 0 )
M_AXIS_TLAST	out	sl
M_AXIS_TDEST	out	slv ( 7 downto 0 )
M_AXIS_TID	out	slv ( 7 downto 0 )
M_AXIS_TUSER	out	slv ( 7 downto 0 )
M_AXIS_TREADY	in	sl := ' 0 '
M_AXI_ARID	out	slv ( 7 downto 0 )
M_AXI_ARADDR	out	slv ( 15 downto 0 )
M_AXI_ARLEN	out	slv ( 7 downto 0 )
M_AXI_ARSIZE	out	slv ( 2 downto 0 )
M_AXI_ARBURST	out	slv ( 1 downto 0 )
M_AXI_ARLOCK	out	sl
M_AXI_ARCACHE	out	slv ( 3 downto 0 )
M_AXI_ARPROT	out	slv ( 2 downto 0 )
M_AXI_ARREGION	out	slv ( 3 downto 0 )
M_AXI_ARQOS	out	slv ( 3 downto 0 )
M_AXI_ARVALID	out	sl
M_AXI_ARREADY	in	sl
M_AXI_RID	in	slv ( 7 downto 0 )
M_AXI_RDATA	in	slv ( DATA_BYTES_G* 8 - 1 downto 0 )
M_AXI_RRESP	in	slv ( 1 downto 0 )
M_AXI_RLAST	in	sl
M_AXI_RVALID	in	sl
M_AXI_RREADY	out	sl

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The documentation for this design unit was generated from the following file:

• axi/dma/ip_integrator/AxiStreamDmaV2ReadIpIntegrator.vhd