AxiStreamBytePackerTbTx.rtl Architecture Reference

Architecture >> AxiStreamBytePackerTbTx::rtl

Processes
comb	( axiRst , r )
seq	( axiClk )
comb	( axiRst , r )
seq	( axiClk )

Constants
REG_INIT_C	RegType := ( byteCount = > 0 , frameCount = > 0 , master = > AXI_STREAM_MASTER_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/AxiStreamBytePackerTbTx.vhd
• protocols/packetizer/tb/AxiStreamBytePackerTbTx.vhd