AxiReadEmulate.structure Architecture Reference

Architecture >> AxiReadEmulate::structure

Processes
comb	( axiRst , intReadMaster , r )
seq	( axiClk )
comb	( axiRst , intReadMaster , r )
seq	( axiClk )

Constants
REG_INIT_C	RegType := ( latency = > 0 , state = > IDLE_S , cnt = > ( others = > ' 0 ' ) , iMaster = > AXI_READ_MASTER_INIT_C , iSlave = > AXI_READ_SLAVE_INIT_C )

Types
StateType	( IDLE_S , DATA_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
intReadMaster	AxiReadMasterType
intReadSlave	AxiReadSlaveType

Records
RegType

Instantiations
u_axireadpathfifo	AxiReadPathFifo <Entity AxiReadPathFifo>
u_axireadpathfifo	AxiReadPathFifo <Entity AxiReadPathFifo>

---

The documentation for this design unit was generated from the following files:

• axi/axi4/rtl/AxiReadEmulate.vhd
• build/SRC_VHDL/surf/AxiReadEmulate.vhd