AxiPkgTb.tb Architecture Reference

Architecture >> AxiPkgTb::tb

Processes
clkproc
seq	( clk )
clkproc
seq	( clk )

Constants
AXI_CFG_C	AxiConfigType := ( ADDR_WIDTH_C = > 32 , DATA_BYTES_C = > 16 , ID_BITS_C = > 5 , LEN_BITS_C = > 8 )

Signals
burstBytes	integer := 4096
totalBytes	slv ( 31 downto 0 ) := X " 7FFF0000 "
address	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
len	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
clk	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• axi/axi4/tb/AxiPkgTb.vhd
• build/SRC_VHDL/surf/AxiPkgTb.vhd