AxiLtc2270DeserBit Entity Reference

Inheritance diagram for AxiLtc2270DeserBit:

Entities
AxiLtc2270DeserBit.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLtc2270Pkg	Package <AxiLtc2270Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
DELAY_INIT_G	slv ( 4 downto 0 ) := ( others = > ' 0 ' )
IODELAY_GROUP_G	string := " AXI_LTC2270_IODELAY_GRP "

Ports
dataP	in	sl
dataN	in	sl
Q1	out	sl
Q2	out	sl
delayInLoad	in	sl
delayInData	in	slv ( 4 downto 0 )
delayOutData	out	slv ( 4 downto 0 )
clk	in	sl
refClk200MHz	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Linear/lct2270/rtl/AxiLtc2270DeserBit.vhd