AxiLitePMbusMasterCore.rtl Architecture Reference

Architecture >> AxiLitePMbusMasterCore::rtl

Processes
comb	( axilReadMaster , axilRst , axilWriteMaster , r , regOut )
seq	( axilClk )

Constants
ACCESS_ROM_C	PMbusAccessArray := ACCESS_ROM_INIT_G
I2C_SCL_5xFREQ_C	real := 5 . 0 * I2C_SCL_FREQ_G
PRESCALE_C	natural := ( getTimeRatio ( AXI_CLK_FREQ_G , I2C_SCL_5xFREQ_C ) ) - 1
FILTER_C	natural := natural ( AXI_CLK_FREQ_G* I2C_MIN_PULSE_G ) + 1
I2C_ADDR_C	slv ( 9 downto 0 ) := ( " 000 " & I2C_ADDR_G )
MY_I2C_REG_MASTER_IN_INIT_C	I2cRegMasterInType := ( i2cAddr = > I2C_ADDR_C , tenbit = > ' 0 ' , regAddr = > ( others = > ' 0 ' ) , regWrData = > ( others = > ' 0 ' ) , regOp = > ' 0 ' , regAddrSkip = > ' 0 ' , regAddrSize = > " 00 " , regDataSize = > " 00 " , regReq = > ' 0 ' , busReq = > ' 0 ' , endianness = > ' 0 ' , repeatStart = > ' 1 ' , wrDataOnRd = > ' 0 ' )
REG_INIT_C	RegType := ( ignoreResp = > ' 1 ' , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , regIn = > MY_I2C_REG_MASTER_IN_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , READ_ACK_S , WRITE_ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
regOut	I2cRegMasterOutType

Attributes
rom_style	string
rom_style	constant is " distributed "
rom_extract	string
rom_extract	constant is " TRUE "
syn_keep	string
syn_keep	constant is " TRUE "

Records
RegType

Instantiations
u_i2cregmaster	I2cRegMaster <Entity I2cRegMaster>

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The documentation for this design unit was generated from the following file:

• protocols/pmbus/rtl/AxiLitePMbusMasterCore.vhd