AxiLiteMaster.rtl Architecture Reference

Architecture >> AxiLiteMaster::rtl

Processes
comb	( axilReadSlave , axilRst , axilWriteSlave , r , req )
seq	( axilClk , axilRst )
comb	( axilReadSlave , axilRst , axilWriteSlave , r , req )
seq	( axilClk , axilRst )

Constants
REG_INIT_C	RegType := ( ack = > AXI_LITE_ACK_INIT_C , state = > S_IDLE_C , axilWriteMaster = > AXI_LITE_WRITE_MASTER_INIT_C , axilReadMaster = > AXI_LITE_READ_MASTER_INIT_C )

Types
StateType	( S_IDLE_C , S_WRITE_C , S_WRITE_AXI_C , S_READ_C , S_READ_AXI_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteMaster.vhd
• build/SRC_VHDL/surf/AxiLiteMaster.vhd