AxiAds42lb69DeserBit Entity Reference

Inheritance diagram for AxiAds42lb69DeserBit:

Collaboration diagram for AxiAds42lb69DeserBit:

Entities
AxiAds42lb69DeserBit.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiAds42lb69Pkg	Package <AxiAds42lb69Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
DELAY_INIT_G	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
IODELAY_GROUP_G	string := " AXI_ADS42LB69_IODELAY_GRP "
XIL_DEVICE_G	string := " 7SERIES "

Ports
dataP	in	sl
dataN	in	sl
Q1	out	sl
Q2	out	sl
delayClk	in	sl
delayRst	in	sl
delayInLoad	in	sl
delayInData	in	slv ( 8 downto 0 )
delayOutData	out	slv ( 9 downto 0 )
clk	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Ti/ads42lb69/rtl/AxiAds42lb69DeserBit.vhd