SURF  1.0
Constants | Types | Signals | Processes
structural Architecture Reference

Processes

gen_clken  ( clk , nReset )
synch_scl_sda  ( clk , nReset )
PROCESS_106  ( clk )
gen_al  ( clk , nReset )
sync_scl_sda  ( clk , nReset , fSCL_chg , fSDA_chg , fiscl_oen_chg , fisda_oen_chg )
PROCESS_107  ( clk )
gen_ald  ( clk , nReset )
detect_sta_sto  ( clk , nReset )
gen_busy  ( clk , nReset )
gen_dout  ( clk )
nxt_state_decoder  ( clk , nReset , c_state , cmd )

Constants

I2C_CMD_NOP  std_logic_vector ( 3 downto 0 ) := " 0000 "
I2C_CMD_START  std_logic_vector ( 3 downto 0 ) := " 0001 "
I2C_CMD_STOP  std_logic_vector ( 3 downto 0 ) := " 0010 "
I2C_CMD_READ  std_logic_vector ( 3 downto 0 ) := " 0100 "
I2C_CMD_WRITE  std_logic_vector ( 3 downto 0 ) := " 1000 "
FR  integer := filter
DR  integer := filter + 1

Types

states ( idle , start_a , start_b , start_c , start_d , start_e , start_f , start_g , stop_a , stop_b , stop_c , stop_d , rd_a , rd_b , rd_c , rd_d , wr_a , wr_b , wr_c , wr_d )

Signals

c_state  states
s_state  states
iscl_oen  std_logic
isda_oen  std_logic
sda_chk  std_logic
fSCL  std_logic_vector ( 1 downto 0 )
fSDA  std_logic_vector ( 1 downto 0 )
clk_en  std_logic
slave_wait  std_logic
ial  std_logic
cnt  std_logic_vector ( 15 downto 0 )
csync  std_logic
sta_condition  std_logic
sto_condition  std_logic
cmd_stop  std_logic
ibusy  std_logic
slvw_dis  std_logic
sSCL  std_logic_vector ( FR downto 0 )
sSDA  std_logic_vector ( FR downto 0 )
discl_oen  std_logic_vector ( DR downto 0 )
disda_oen  std_logic_vector ( DR downto 0 )
filtcnt  std_logic_vector ( filter - 1 downto 0 )
sSCL  std_logic_vector ( 1 downto 0 )
sSDA  std_logic_vector ( 1 downto 0 )
fiscl_oen  std_logic_vector ( 1 downto 0 )
fisda_oen  std_ulogic
fSCL_chg  std_ulogic
fSDA_chg  std_ulogic
fiscl_oen_chg  std_ulogic
fisda_oen_chg  std_ulogic
discl_oen  std_ulogic
disda_oen  std_ulogic

Detailed Description

Definition at line 206 of file i2c_master_bit_ctrl.vhd.

Member Function Documentation

◆ gen_clken()

gen_clken (   clk ,
  nReset  
)
Process

Definition at line 227 of file i2c_master_bit_ctrl.vhd.

◆ synch_scl_sda()

synch_scl_sda (   clk ,
  nReset  
)
Process

Definition at line 365 of file i2c_master_bit_ctrl.vhd.

◆ PROCESS_106()

PROCESS_106 (   clk  
)
Process

Definition at line 365 of file i2c_master_bit_ctrl.vhd.

◆ gen_al()

gen_al (   clk ,
  nReset  
)
Process

Definition at line 365 of file i2c_master_bit_ctrl.vhd.

◆ sync_scl_sda()

sync_scl_sda (   clk ,
  nReset ,
  fSCL_chg ,
  fSDA_chg ,
  fiscl_oen_chg ,
  fisda_oen_chg  
)
Process

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ PROCESS_107()

PROCESS_107 (   clk  
)
Process

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ gen_ald()

gen_ald (   clk ,
  nReset  
)
Process

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ detect_sta_sto()

detect_sta_sto (   clk ,
  nReset  
)
Process

Definition at line 490 of file i2c_master_bit_ctrl.vhd.

◆ gen_busy()

gen_busy (   clk ,
  nReset  
)
Process

Definition at line 515 of file i2c_master_bit_ctrl.vhd.

◆ gen_dout()

gen_dout (   clk  
)
Process

Definition at line 530 of file i2c_master_bit_ctrl.vhd.

◆ nxt_state_decoder()

nxt_state_decoder (   clk ,
  nReset ,
  c_state ,
  cmd  
)
Process

Definition at line 542 of file i2c_master_bit_ctrl.vhd.

Member Data Documentation

◆ I2C_CMD_NOP

I2C_CMD_NOP std_logic_vector ( 3 downto 0 ) := " 0000 "
Constant

Definition at line 207 of file i2c_master_bit_ctrl.vhd.

◆ I2C_CMD_START

I2C_CMD_START std_logic_vector ( 3 downto 0 ) := " 0001 "
Constant

Definition at line 208 of file i2c_master_bit_ctrl.vhd.

◆ I2C_CMD_STOP

I2C_CMD_STOP std_logic_vector ( 3 downto 0 ) := " 0010 "
Constant

Definition at line 209 of file i2c_master_bit_ctrl.vhd.

◆ I2C_CMD_READ

I2C_CMD_READ std_logic_vector ( 3 downto 0 ) := " 0100 "
Constant

Definition at line 210 of file i2c_master_bit_ctrl.vhd.

◆ I2C_CMD_WRITE

I2C_CMD_WRITE std_logic_vector ( 3 downto 0 ) := " 1000 "
Constant

Definition at line 211 of file i2c_master_bit_ctrl.vhd.

◆ states

states ( idle , start_a , start_b , start_c , start_d , start_e , start_f , start_g , stop_a , stop_b , stop_c , stop_d , rd_a , rd_b , rd_c , rd_d , wr_a , wr_b , wr_c , wr_d )
Type

Definition at line 213 of file i2c_master_bit_ctrl.vhd.

◆ c_state

c_state states
Signal

Definition at line 215 of file i2c_master_bit_ctrl.vhd.

◆ s_state

s_state states
Signal

Definition at line 215 of file i2c_master_bit_ctrl.vhd.

◆ iscl_oen

iscl_oen std_logic
Signal

Definition at line 217 of file i2c_master_bit_ctrl.vhd.

◆ isda_oen

isda_oen std_logic
Signal

Definition at line 217 of file i2c_master_bit_ctrl.vhd.

◆ sda_chk

sda_chk std_logic
Signal

Definition at line 218 of file i2c_master_bit_ctrl.vhd.

◆ fSCL

fSCL std_logic_vector ( 1 downto 0 )
Signal

Definition at line 219 of file i2c_master_bit_ctrl.vhd.

◆ fSDA

fSDA std_logic_vector ( 1 downto 0 )
Signal

Definition at line 219 of file i2c_master_bit_ctrl.vhd.

◆ clk_en

clk_en std_logic
Signal

Definition at line 220 of file i2c_master_bit_ctrl.vhd.

◆ slave_wait

slave_wait std_logic
Signal

Definition at line 220 of file i2c_master_bit_ctrl.vhd.

◆ ial

ial std_logic
Signal

Definition at line 221 of file i2c_master_bit_ctrl.vhd.

◆ cnt

cnt std_logic_vector ( 15 downto 0 )
Signal

Definition at line 222 of file i2c_master_bit_ctrl.vhd.

◆ csync

csync std_logic
Signal

Definition at line 223 of file i2c_master_bit_ctrl.vhd.

◆ sta_condition

sta_condition std_logic
Signal

Definition at line 255 of file i2c_master_bit_ctrl.vhd.

◆ sto_condition

sto_condition std_logic
Signal

Definition at line 256 of file i2c_master_bit_ctrl.vhd.

◆ cmd_stop

cmd_stop std_logic
Signal

Definition at line 257 of file i2c_master_bit_ctrl.vhd.

◆ ibusy

ibusy std_logic
Signal

Definition at line 258 of file i2c_master_bit_ctrl.vhd.

◆ slvw_dis

slvw_dis std_logic
Signal

Definition at line 259 of file i2c_master_bit_ctrl.vhd.

◆ FR

FR integer := filter
Constant

Definition at line 266 of file i2c_master_bit_ctrl.vhd.

◆ DR

DR integer := filter + 1
Constant

Definition at line 266 of file i2c_master_bit_ctrl.vhd.

◆ sSCL [1/2]

sSCL std_logic_vector ( FR downto 0 )
Signal

Definition at line 365 of file i2c_master_bit_ctrl.vhd.

◆ sSDA [1/2]

sSDA std_logic_vector ( FR downto 0 )
Signal

Definition at line 365 of file i2c_master_bit_ctrl.vhd.

◆ discl_oen [1/2]

discl_oen std_logic_vector ( DR downto 0 )
Signal

Definition at line 365 of file i2c_master_bit_ctrl.vhd.

◆ disda_oen [1/2]

disda_oen std_logic_vector ( DR downto 0 )
Signal

Definition at line 365 of file i2c_master_bit_ctrl.vhd.

◆ filtcnt

filtcnt std_logic_vector ( filter - 1 downto 0 )
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ sSCL [2/2]

sSCL std_logic_vector ( 1 downto 0 )
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ sSDA [2/2]

sSDA std_logic_vector ( 1 downto 0 )
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ fiscl_oen

fiscl_oen std_logic_vector ( 1 downto 0 )
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ fisda_oen

fisda_oen std_ulogic
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ fSCL_chg

fSCL_chg std_ulogic
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ fSDA_chg

fSDA_chg std_ulogic
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ fiscl_oen_chg

fiscl_oen_chg std_ulogic
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ fisda_oen_chg

fisda_oen_chg std_ulogic
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ discl_oen [2/2]

discl_oen std_ulogic
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

◆ disda_oen [2/2]

disda_oen std_ulogic
Signal

Definition at line 484 of file i2c_master_bit_ctrl.vhd.

The documentation for this class was generated from the following file: