SURF  1.0
Generics | Ports | Libraries | Use Clauses
adc32rf45 Entity Reference
devices » Ti » adc32rf45
+ Inheritance diagram for adc32rf45:
+ Collaboration diagram for adc32rf45:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
CLK_PERIOD_G  real := ( 1 . 0 / 156 . 25E + 6 )
SPI_SCLK_PERIOD_G  real := ( 1 . 0 / 10 . 0E + 6 )

Ports

axiClk   in sl
axiRst   in sl
axiReadMaster   in AxiLiteReadMasterType
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType
axiWriteSlave   out AxiLiteWriteSlaveType
coreRst   out sl
coreSclk   out sl
coreSDin   in sl
coreSDout   out sl
coreCsb   out sl

Detailed Description

See also
entity

Definition at line 28 of file adc32rf45.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file adc32rf45.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
Generic

Definition at line 31 of file adc32rf45.vhd.

◆ CLK_PERIOD_G

CLK_PERIOD_G real := ( 1 . 0 / 156 . 25E + 6 )
Generic

Definition at line 32 of file adc32rf45.vhd.

◆ SPI_SCLK_PERIOD_G

SPI_SCLK_PERIOD_G real := ( 1 . 0 / 10 . 0E + 6 )
Generic

Definition at line 33 of file adc32rf45.vhd.

◆ axiClk

axiClk in sl
Port

Definition at line 36 of file adc32rf45.vhd.

◆ axiRst

axiRst in sl
Port

Definition at line 37 of file adc32rf45.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType
Port

Definition at line 39 of file adc32rf45.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 40 of file adc32rf45.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType
Port

Definition at line 41 of file adc32rf45.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 42 of file adc32rf45.vhd.

◆ coreRst

coreRst out sl
Port

Definition at line 44 of file adc32rf45.vhd.

◆ coreSclk

coreSclk out sl
Port

Definition at line 45 of file adc32rf45.vhd.

◆ coreSDin

coreSDin in sl
Port

Definition at line 46 of file adc32rf45.vhd.

◆ coreSDout

coreSDout out sl
Port

Definition at line 47 of file adc32rf45.vhd.

◆ coreCsb

coreCsb out sl
Port

Definition at line 48 of file adc32rf45.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file adc32rf45.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file adc32rf45.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file adc32rf45.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file adc32rf45.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 23 of file adc32rf45.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file adc32rf45.vhd.

The documentation for this class was generated from the following file: