Inheritance diagram for UartSem:
Collaboration diagram for UartSem:
Entities | |
| mapping | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| SemPkg | Package <SemPkg> |
Generics | |
| TPD_G | time := 1 ns |
| CLK_FREQ_G | real := 100 . 0E + 6 |
| BAUD_RATE_G | positive := 115200 |
| FIFO_BRAM_EN_G | boolean := false |
| FIFO_ADDR_WIDTH_G | positive := 5 |
Ports | |
| semClk | in sl |
| semRst | in sl |
| fpgaReload | in sl := ' 0 ' |
| fpgaReloadAddr | in slv ( 31 downto 0 ) := ( others = > ' 0 ' ) |
| uartTx | out sl |
| uartRx | in sl |
Detailed Description
- See also
- entity
Definition at line 28 of file UartSem.vhd.
Member Data Documentation
◆ TPD_G
|
Generic |
Definition at line 30 of file UartSem.vhd.
◆ CLK_FREQ_G
|
Generic |
Definition at line 31 of file UartSem.vhd.
◆ BAUD_RATE_G
|
Generic |
Definition at line 32 of file UartSem.vhd.
◆ FIFO_BRAM_EN_G
|
Generic |
Definition at line 33 of file UartSem.vhd.
◆ FIFO_ADDR_WIDTH_G
|
Generic |
Definition at line 34 of file UartSem.vhd.
◆ semClk
Definition at line 37 of file UartSem.vhd.
◆ semRst
Definition at line 38 of file UartSem.vhd.
◆ fpgaReload
|
Port |
Definition at line 40 of file UartSem.vhd.
◆ fpgaReloadAddr
|
Port |
Definition at line 41 of file UartSem.vhd.
◆ uartTx
Definition at line 43 of file UartSem.vhd.
◆ uartRx
Definition at line 44 of file UartSem.vhd.
◆ ieee
|
Library |
Definition at line 18 of file UartSem.vhd.
◆ std_logic_1164
|
Package |
Definition at line 19 of file UartSem.vhd.
◆ std_logic_unsigned
|
Package |
Definition at line 20 of file UartSem.vhd.
◆ std_logic_arith
|
Package |
Definition at line 21 of file UartSem.vhd.
◆ StdRtlPkg
|
Package |
Definition at line 23 of file UartSem.vhd.
◆ SemPkg
|
Package |
Definition at line 24 of file UartSem.vhd.
The documentation for this class was generated from the following file:
- xilinx/7Series/sem/rtl/UartSem.vhd
