SURF  1.0
Generics | Ports | Libraries | Use Clauses
UartAxiLiteMaster Entity Reference
protocols » uart
+ Inheritance diagram for UartAxiLiteMaster:
+ Collaboration diagram for UartAxiLiteMaster:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
TextUtilPkg  Package <TextUtilPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiLiteMasterPkg  Package <AxiLiteMasterPkg>

Generics

TPD_G  time := 1 ns
AXIL_CLK_FREQ_G  real := 125 . 0e6
BAUD_RATE_G  integer := 115200
FIFO_BRAM_EN_G  boolean := false
FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 5

Ports

axilClk   in sl
axilRst   in sl
mAxilWriteMaster   out AxiLiteWriteMasterType
mAxilWriteSlave   in AxiLiteWriteSlaveType
mAxilReadMaster   out AxiLiteReadMasterType
mAxilReadSlave   in AxiLiteReadSlaveType
tx   out sl
rx   in sl

Detailed Description

See also
entity

Definition at line 31 of file UartAxiLiteMaster.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file UartAxiLiteMaster.vhd.

◆ AXIL_CLK_FREQ_G

AXIL_CLK_FREQ_G real := 125 . 0e6
Generic

Definition at line 35 of file UartAxiLiteMaster.vhd.

◆ BAUD_RATE_G

BAUD_RATE_G integer := 115200
Generic

Definition at line 36 of file UartAxiLiteMaster.vhd.

◆ FIFO_BRAM_EN_G

FIFO_BRAM_EN_G boolean := false
Generic

Definition at line 37 of file UartAxiLiteMaster.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G integer range 4 to 48 := 5
Generic

Definition at line 38 of file UartAxiLiteMaster.vhd.

◆ axilClk

axilClk in sl
Port

Definition at line 40 of file UartAxiLiteMaster.vhd.

◆ axilRst

axilRst in sl
Port

Definition at line 41 of file UartAxiLiteMaster.vhd.

◆ mAxilWriteMaster

mAxilWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 43 of file UartAxiLiteMaster.vhd.

◆ mAxilWriteSlave

mAxilWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 44 of file UartAxiLiteMaster.vhd.

◆ mAxilReadMaster

mAxilReadMaster out AxiLiteReadMasterType
Port

Definition at line 45 of file UartAxiLiteMaster.vhd.

◆ mAxilReadSlave

mAxilReadSlave in AxiLiteReadSlaveType
Port

Definition at line 46 of file UartAxiLiteMaster.vhd.

◆ tx

tx out sl
Port

Definition at line 48 of file UartAxiLiteMaster.vhd.

◆ rx

rx in sl
Port

Definition at line 49 of file UartAxiLiteMaster.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file UartAxiLiteMaster.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file UartAxiLiteMaster.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 21 of file UartAxiLiteMaster.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 22 of file UartAxiLiteMaster.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file UartAxiLiteMaster.vhd.

◆ TextUtilPkg

TextUtilPkg
Package

Definition at line 25 of file UartAxiLiteMaster.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 26 of file UartAxiLiteMaster.vhd.

◆ AxiLiteMasterPkg

AxiLiteMasterPkg
Package

Definition at line 27 of file UartAxiLiteMaster.vhd.

The documentation for this class was generated from the following file: