SURF  1.0
Generics | Ports | Libraries | Use Clauses
TrueDualPortRam Entity Reference
base » ram
+ Inheritance diagram for TrueDualPortRam:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>

Generics

TPD_G  time := 1 ns
RST_POLARITY_G  sl := ' 1 '
ALTERA_RAM_G  string := " M9K "
DOA_REG_G  boolean := false
DOB_REG_G  boolean := false
MODE_G  string := " read-first "
BYTE_WR_EN_G  boolean := false
DATA_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 18
BYTE_WIDTH_G  integer := 8
ADDR_WIDTH_G  integer range 1 to ( 2 ** 24 ) := 9
INIT_G  slv := " 0 "

Ports

clka   in sl := ' 0 '
ena   in sl := ' 1 '
wea   in sl := ' 0 '
weaByte   in slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
rsta   in sl := not ( RST_POLARITY_G )
addra   in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
dina   in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
douta   out slv ( DATA_WIDTH_G - 1 downto 0 )
regcea   in sl := ' 1 '
clkb   in sl := ' 0 '
enb   in sl := ' 1 '
web   in sl := ' 0 '
webByte   in slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
rstb   in sl := not ( RST_POLARITY_G )
addrb   in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
dinb   in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
doutb   out slv ( DATA_WIDTH_G - 1 downto 0 )
regceb   in sl := ' 1 '

Detailed Description

See also
entity

Definition at line 28 of file TrueDualPortRam.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file TrueDualPortRam.vhd.

◆ RST_POLARITY_G

RST_POLARITY_G sl := ' 1 '
Generic

Definition at line 32 of file TrueDualPortRam.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 33 of file TrueDualPortRam.vhd.

◆ DOA_REG_G

DOA_REG_G boolean := false
Generic

Definition at line 34 of file TrueDualPortRam.vhd.

◆ DOB_REG_G

DOB_REG_G boolean := false
Generic

Definition at line 35 of file TrueDualPortRam.vhd.

◆ MODE_G

MODE_G string := " read-first "
Generic

Definition at line 36 of file TrueDualPortRam.vhd.

◆ BYTE_WR_EN_G

BYTE_WR_EN_G boolean := false
Generic

Definition at line 37 of file TrueDualPortRam.vhd.

◆ DATA_WIDTH_G

DATA_WIDTH_G integer range 1 to ( 2 ** 24 ) := 18
Generic

Definition at line 38 of file TrueDualPortRam.vhd.

◆ BYTE_WIDTH_G

BYTE_WIDTH_G integer := 8
Generic

Definition at line 39 of file TrueDualPortRam.vhd.

◆ ADDR_WIDTH_G

ADDR_WIDTH_G integer range 1 to ( 2 ** 24 ) := 9
Generic

Definition at line 40 of file TrueDualPortRam.vhd.

◆ INIT_G

INIT_G slv := " 0 "
Generic

Definition at line 41 of file TrueDualPortRam.vhd.

◆ clka

clka in sl := ' 0 '
Port

Definition at line 44 of file TrueDualPortRam.vhd.

◆ ena

ena in sl := ' 1 '
Port

Definition at line 45 of file TrueDualPortRam.vhd.

◆ wea

wea in sl := ' 0 '
Port

Definition at line 46 of file TrueDualPortRam.vhd.

◆ weaByte

weaByte in slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 47 of file TrueDualPortRam.vhd.

◆ rsta

rsta in sl := not ( RST_POLARITY_G )
Port

Definition at line 48 of file TrueDualPortRam.vhd.

◆ addra

addra in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 49 of file TrueDualPortRam.vhd.

◆ dina

dina in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 50 of file TrueDualPortRam.vhd.

◆ douta

douta out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 51 of file TrueDualPortRam.vhd.

◆ regcea

regcea in sl := ' 1 '
Port

Definition at line 52 of file TrueDualPortRam.vhd.

◆ clkb

clkb in sl := ' 0 '
Port

Definition at line 54 of file TrueDualPortRam.vhd.

◆ enb

enb in sl := ' 1 '
Port

Definition at line 55 of file TrueDualPortRam.vhd.

◆ web

web in sl := ' 0 '
Port

Definition at line 56 of file TrueDualPortRam.vhd.

◆ webByte

webByte in slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 57 of file TrueDualPortRam.vhd.

◆ rstb

rstb in sl := not ( RST_POLARITY_G )
Port

Definition at line 58 of file TrueDualPortRam.vhd.

◆ addrb

addrb in slv ( ADDR_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 59 of file TrueDualPortRam.vhd.

◆ dinb

dinb in slv ( DATA_WIDTH_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 60 of file TrueDualPortRam.vhd.

◆ doutb

doutb out slv ( DATA_WIDTH_G - 1 downto 0 )
Port

Definition at line 61 of file TrueDualPortRam.vhd.

◆ regceb

regceb in sl := ' 1 '
Port

Definition at line 62 of file TrueDualPortRam.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file TrueDualPortRam.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file TrueDualPortRam.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 22 of file TrueDualPortRam.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file TrueDualPortRam.vhd.

The documentation for this class was generated from the following file: