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TenGigEthGthUltraScaleWrapper Entity Reference
ethernet » TenGigEthCore » gthUltraScale
+ Inheritance diagram for TenGigEthGthUltraScaleWrapper:
+ Collaboration diagram for TenGigEthGthUltraScaleWrapper:

Entities

mapping  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
AxiLitePkg  Package <AxiLitePkg>
TenGigEthPkg  Package <TenGigEthPkg>

Generics

TPD_G  time := 1 ns
REF_CLK_FREQ_G  real := 156 . 25E + 6
NUM_LANE_G  natural range 1 to 4 := 1
QPLL_REFCLK_SEL_G  slv ( 2 downto 0 ) := " 001 "
EN_AXI_REG_G  boolean := false
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
AXIS_CONFIG_G  AxiStreamConfigArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CONFIG_INIT_C )

Ports

localMac   in Slv48Array ( NUM_LANE_G - 1 downto 0 ) := ( others = > MAC_ADDR_INIT_C )
dmaClk   in slv ( NUM_LANE_G - 1 downto 0 )
dmaRst   in slv ( NUM_LANE_G - 1 downto 0 )
dmaIbMasters   out AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
dmaIbSlaves   in AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
dmaObMasters   in AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
dmaObSlaves   out AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
axiLiteClk   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
axiLiteRst   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
axiLiteReadMasters   in AxiLiteReadMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
axiLiteReadSlaves   out AxiLiteReadSlaveArray ( NUM_LANE_G - 1 downto 0 )
axiLiteWriteMasters   in AxiLiteWriteMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
axiLiteWriteSlaves   out AxiLiteWriteSlaveArray ( NUM_LANE_G - 1 downto 0 )
sigDet   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 1 ' )
txFault   in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
txDisable   out slv ( NUM_LANE_G - 1 downto 0 )
extRst   in sl
coreClk   out sl
coreRst   out sl
phyClk   out slv ( NUM_LANE_G - 1 downto 0 )
phyRst   out slv ( NUM_LANE_G - 1 downto 0 )
phyReady   out slv ( NUM_LANE_G - 1 downto 0 )
gtClk   out sl
gtTxPreCursor   in slv ( 4 downto 0 ) := " 00000 "
gtTxPostCursor   in slv ( 4 downto 0 ) := " 00000 "
gtTxDiffCtrl   in slv ( 3 downto 0 ) := " 1110 "
gtRxPolarity   in sl := ' 0 '
gtTxPolarity   in sl := ' 0 '
gtRefClk   in sl := ' 0 '
gtClkP   in sl := ' 1 '
gtClkN   in sl := ' 0 '
gtTxP   out slv ( NUM_LANE_G - 1 downto 0 )
gtTxN   out slv ( NUM_LANE_G - 1 downto 0 )
gtRxP   in slv ( NUM_LANE_G - 1 downto 0 )
gtRxN   in slv ( NUM_LANE_G - 1 downto 0 )

Detailed Description

See also
entity

Definition at line 29 of file TenGigEthGthUltraScaleWrapper.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 31 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ REF_CLK_FREQ_G

REF_CLK_FREQ_G real := 156 . 25E + 6
Generic

Definition at line 32 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ NUM_LANE_G

NUM_LANE_G natural range 1 to 4 := 1
Generic

Definition at line 33 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ QPLL_REFCLK_SEL_G

QPLL_REFCLK_SEL_G slv ( 2 downto 0 ) := " 001 "
Generic

Definition at line 35 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ EN_AXI_REG_G

EN_AXI_REG_G boolean := false
Generic

Definition at line 37 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 38 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ AXIS_CONFIG_G

AXIS_CONFIG_G AxiStreamConfigArray ( 3 downto 0 ) := ( others = > AXI_STREAM_CONFIG_INIT_C )
Generic

Definition at line 40 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ localMac

localMac in Slv48Array ( NUM_LANE_G - 1 downto 0 ) := ( others = > MAC_ADDR_INIT_C )
Port

Definition at line 43 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ dmaClk

dmaClk in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 45 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ dmaRst

dmaRst in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 46 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ dmaIbMasters

dmaIbMasters out AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 47 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ dmaIbSlaves

dmaIbSlaves in AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 48 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ dmaObMasters

dmaObMasters in AxiStreamMasterArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 49 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ dmaObSlaves

dmaObSlaves out AxiStreamSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 50 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ axiLiteClk

axiLiteClk in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 52 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ axiLiteRst

axiLiteRst in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 53 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ axiLiteReadMasters

axiLiteReadMasters in AxiLiteReadMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_READ_MASTER_INIT_C )
Port

Definition at line 54 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ axiLiteReadSlaves

axiLiteReadSlaves out AxiLiteReadSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 55 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ axiLiteWriteMasters

axiLiteWriteMasters in AxiLiteWriteMasterArray ( NUM_LANE_G - 1 downto 0 ) := ( others = > AXI_LITE_WRITE_MASTER_INIT_C )
Port

Definition at line 56 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ axiLiteWriteSlaves

axiLiteWriteSlaves out AxiLiteWriteSlaveArray ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 57 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ sigDet

sigDet in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 1 ' )
Port

Definition at line 59 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ txFault

txFault in slv ( NUM_LANE_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 60 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ txDisable

txDisable out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 61 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ extRst

extRst in sl
Port

Definition at line 63 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ coreClk

coreClk out sl
Port

Definition at line 64 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ coreRst

coreRst out sl
Port

Definition at line 65 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ phyClk

phyClk out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 66 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ phyRst

phyRst out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 67 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ phyReady

phyReady out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 68 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtClk

gtClk out sl
Port

Definition at line 69 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtTxPreCursor

gtTxPreCursor in slv ( 4 downto 0 ) := " 00000 "
Port

Definition at line 71 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtTxPostCursor

gtTxPostCursor in slv ( 4 downto 0 ) := " 00000 "
Port

Definition at line 72 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtTxDiffCtrl

gtTxDiffCtrl in slv ( 3 downto 0 ) := " 1110 "
Port

Definition at line 73 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtRxPolarity

gtRxPolarity in sl := ' 0 '
Port

Definition at line 74 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtTxPolarity

gtTxPolarity in sl := ' 0 '
Port

Definition at line 75 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtRefClk

gtRefClk in sl := ' 0 '
Port

Definition at line 77 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtClkP

gtClkP in sl := ' 1 '
Port

Definition at line 78 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtClkN

gtClkN in sl := ' 0 '
Port

Definition at line 79 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtTxP

gtTxP out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 81 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtTxN

gtTxN out slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 82 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtRxP

gtRxP in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 83 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ gtRxN

gtRxN in slv ( NUM_LANE_G - 1 downto 0 )
Port

Definition at line 84 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 23 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 24 of file TenGigEthGthUltraScaleWrapper.vhd.

◆ TenGigEthPkg

TenGigEthPkg
Package

Definition at line 25 of file TenGigEthGthUltraScaleWrapper.vhd.

The documentation for this class was generated from the following file: