SURF  1.0
Generics | Ports | Libraries | Use Clauses
SsiPrbsTxOld Entity Reference
protocols » ssi
+ Inheritance diagram for SsiPrbsTxOld:
+ Collaboration diagram for SsiPrbsTxOld:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>

Generics

TPD_G  time := 1 ns
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
CASCADE_SIZE_G  natural range 1 to ( 2 ** 24 ) := 1
FIFO_ADDR_WIDTH_G  natural range 4 to 48 := 9
FIFO_PAUSE_THRESH_G  natural range 1 to ( 2 ** 24 ) := 2 ** 8
PRBS_SEED_SIZE_G  natural range 32 to 128 := 32
PRBS_TAPS_G  NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
MASTER_AXI_STREAM_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 16 , TKEEP_COMP_C )
MASTER_AXI_PIPE_STAGES_G  natural range 0 to 16 := 0

Ports

mAxisClk   in sl
mAxisRst   in sl
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
locClk   in sl
locRst   in sl := ' 0 '
trig   in sl := ' 1 '
packetLength   in slv ( 31 downto 0 ) := X " FFFFFFFF "
forceEofe   in sl := ' 0 '
busy   out sl
tDest   in slv ( 7 downto 0 ) := X " 00 "
tId   in slv ( 7 downto 0 ) := X " 00 "

Detailed Description

See also
entity

Definition at line 30 of file SsiPrbsTxOld.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file SsiPrbsTxOld.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 35 of file SsiPrbsTxOld.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 36 of file SsiPrbsTxOld.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 37 of file SsiPrbsTxOld.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 38 of file SsiPrbsTxOld.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 39 of file SsiPrbsTxOld.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 40 of file SsiPrbsTxOld.vhd.

◆ CASCADE_SIZE_G

CASCADE_SIZE_G natural range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 41 of file SsiPrbsTxOld.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G natural range 4 to 48 := 9
Generic

Definition at line 42 of file SsiPrbsTxOld.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G natural range 1 to ( 2 ** 24 ) := 2 ** 8
Generic

Definition at line 43 of file SsiPrbsTxOld.vhd.

◆ PRBS_SEED_SIZE_G

PRBS_SEED_SIZE_G natural range 32 to 128 := 32
Generic

Definition at line 45 of file SsiPrbsTxOld.vhd.

◆ PRBS_TAPS_G

PRBS_TAPS_G NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
Generic

Definition at line 46 of file SsiPrbsTxOld.vhd.

◆ MASTER_AXI_STREAM_CONFIG_G

MASTER_AXI_STREAM_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 16 , TKEEP_COMP_C )
Generic

Definition at line 48 of file SsiPrbsTxOld.vhd.

◆ MASTER_AXI_PIPE_STAGES_G

MASTER_AXI_PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 49 of file SsiPrbsTxOld.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 52 of file SsiPrbsTxOld.vhd.

◆ mAxisRst

mAxisRst in sl
Port

Definition at line 53 of file SsiPrbsTxOld.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 54 of file SsiPrbsTxOld.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 55 of file SsiPrbsTxOld.vhd.

◆ locClk

locClk in sl
Port

Definition at line 57 of file SsiPrbsTxOld.vhd.

◆ locRst

locRst in sl := ' 0 '
Port

Definition at line 58 of file SsiPrbsTxOld.vhd.

◆ trig

trig in sl := ' 1 '
Port

Definition at line 59 of file SsiPrbsTxOld.vhd.

◆ packetLength

packetLength in slv ( 31 downto 0 ) := X " FFFFFFFF "
Port

Definition at line 60 of file SsiPrbsTxOld.vhd.

◆ forceEofe

forceEofe in sl := ' 0 '
Port

Definition at line 61 of file SsiPrbsTxOld.vhd.

◆ busy

busy out sl
Port

Definition at line 62 of file SsiPrbsTxOld.vhd.

◆ tDest

tDest in slv ( 7 downto 0 ) := X " 00 "
Port

Definition at line 63 of file SsiPrbsTxOld.vhd.

◆ tId

tId in slv ( 7 downto 0 ) := X " 00 "
Port

Definition at line 64 of file SsiPrbsTxOld.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file SsiPrbsTxOld.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file SsiPrbsTxOld.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file SsiPrbsTxOld.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file SsiPrbsTxOld.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file SsiPrbsTxOld.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 25 of file SsiPrbsTxOld.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 26 of file SsiPrbsTxOld.vhd.

The documentation for this class was generated from the following file: