SURF  1.0
SsiPrbsTx Entity Reference
+ Inheritance diagram for SsiPrbsTx:
+ Collaboration diagram for SsiPrbsTx:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
VALID_THOLD_G  integer range 0 to ( 2 ** 24 ) := 1
VALID_BURST_MODE_G  boolean := false
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
CASCADE_SIZE_G  natural range 1 to ( 2 ** 24 ) := 1
FIFO_ADDR_WIDTH_G  natural range 4 to 48 := 9
FIFO_PAUSE_THRESH_G  natural range 1 to ( 2 ** 24 ) := 2 ** 8
PRBS_SEED_SIZE_G  natural range 8 to 128 := 32
PRBS_TAPS_G  NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
PRBS_INCREMENT_G  boolean := false
MASTER_AXI_STREAM_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 16 , TKEEP_COMP_C )
MASTER_AXI_PIPE_STAGES_G  natural range 0 to 16 := 0

Ports

mAxisClk   in sl
mAxisRst   in sl
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
locClk   in sl
locRst   in sl := ' 0 '
trig   in sl := ' 1 '
packetLength   in slv ( 31 downto 0 ) := X " FFFFFFFF "
forceEofe   in sl := ' 0 '
busy   out sl
tDest   in slv ( 7 downto 0 ) := X " 00 "
tId   in slv ( 7 downto 0 ) := X " 00 "
axilReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 31 of file SsiPrbsTx.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file SsiPrbsTx.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 35 of file SsiPrbsTx.vhd.

◆ VALID_THOLD_G

VALID_THOLD_G integer range 0 to ( 2 ** 24 ) := 1
Generic

Definition at line 37 of file SsiPrbsTx.vhd.

◆ VALID_BURST_MODE_G

VALID_BURST_MODE_G boolean := false
Generic

Definition at line 38 of file SsiPrbsTx.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 39 of file SsiPrbsTx.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 40 of file SsiPrbsTx.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 41 of file SsiPrbsTx.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 42 of file SsiPrbsTx.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 43 of file SsiPrbsTx.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 44 of file SsiPrbsTx.vhd.

◆ CASCADE_SIZE_G

CASCADE_SIZE_G natural range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 45 of file SsiPrbsTx.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G natural range 4 to 48 := 9
Generic

Definition at line 46 of file SsiPrbsTx.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G natural range 1 to ( 2 ** 24 ) := 2 ** 8
Generic

Definition at line 47 of file SsiPrbsTx.vhd.

◆ PRBS_SEED_SIZE_G

PRBS_SEED_SIZE_G natural range 8 to 128 := 32
Generic

Definition at line 49 of file SsiPrbsTx.vhd.

◆ PRBS_TAPS_G

PRBS_TAPS_G NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
Generic

Definition at line 50 of file SsiPrbsTx.vhd.

◆ PRBS_INCREMENT_G

PRBS_INCREMENT_G boolean := false
Generic

Definition at line 51 of file SsiPrbsTx.vhd.

◆ MASTER_AXI_STREAM_CONFIG_G

MASTER_AXI_STREAM_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 16 , TKEEP_COMP_C )
Generic

Definition at line 53 of file SsiPrbsTx.vhd.

◆ MASTER_AXI_PIPE_STAGES_G

MASTER_AXI_PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 54 of file SsiPrbsTx.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 57 of file SsiPrbsTx.vhd.

◆ mAxisRst

mAxisRst in sl
Port

Definition at line 58 of file SsiPrbsTx.vhd.

◆ mAxisMaster

Definition at line 59 of file SsiPrbsTx.vhd.

◆ mAxisSlave

Definition at line 60 of file SsiPrbsTx.vhd.

◆ locClk

locClk in sl
Port

Definition at line 62 of file SsiPrbsTx.vhd.

◆ locRst

locRst in sl := ' 0 '
Port

Definition at line 63 of file SsiPrbsTx.vhd.

◆ trig

trig in sl := ' 1 '
Port

Definition at line 64 of file SsiPrbsTx.vhd.

◆ packetLength

packetLength in slv ( 31 downto 0 ) := X " FFFFFFFF "
Port

Definition at line 65 of file SsiPrbsTx.vhd.

◆ forceEofe

forceEofe in sl := ' 0 '
Port

Definition at line 66 of file SsiPrbsTx.vhd.

◆ busy

busy out sl
Port

Definition at line 67 of file SsiPrbsTx.vhd.

◆ tDest

tDest in slv ( 7 downto 0 ) := X " 00 "
Port

Definition at line 68 of file SsiPrbsTx.vhd.

◆ tId

tId in slv ( 7 downto 0 ) := X " 00 "
Port

Definition at line 69 of file SsiPrbsTx.vhd.

◆ axilReadMaster

◆ axilReadSlave

Definition at line 72 of file SsiPrbsTx.vhd.

◆ axilWriteMaster

◆ axilWriteSlave

Definition at line 74 of file SsiPrbsTx.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file SsiPrbsTx.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file SsiPrbsTx.vhd.

◆ std_logic_unsigned

Definition at line 21 of file SsiPrbsTx.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file SsiPrbsTx.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file SsiPrbsTx.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 25 of file SsiPrbsTx.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 26 of file SsiPrbsTx.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 27 of file SsiPrbsTx.vhd.


The documentation for this class was generated from the following file: