SURF  1.0
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SsiPrbsRx Entity Reference
protocols » ssi
+ Inheritance diagram for SsiPrbsRx:
+ Collaboration diagram for SsiPrbsRx:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>

Generics

TPD_G  time := 1 ns
STATUS_CNT_WIDTH_G  natural range 1 to 32 := 32
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
GEN_SYNC_FIFO_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
CASCADE_SIZE_G  natural range 1 to ( 2 ** 24 ) := 1
FIFO_ADDR_WIDTH_G  natural range 4 to 48 := 9
FIFO_PAUSE_THRESH_G  natural range 1 to ( 2 ** 24 ) := 2 ** 8
PRBS_SEED_SIZE_G  natural range 8 to 128 := 32
PRBS_TAPS_G  NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
SLAVE_AXI_STREAM_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
SLAVE_AXI_PIPE_STAGES_G  natural range 0 to 16 := 0
MASTER_AXI_STREAM_CONFIG_G  AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
MASTER_AXI_PIPE_STAGES_G  natural range 0 to 16 := 0

Ports

sAxisClk   in sl
sAxisRst   in sl := ' 0 '
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
sAxisCtrl   out AxiStreamCtrlType
mAxisClk   in sl
mAxisRst   in sl := ' 0 '
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
axiClk   in sl := ' 0 '
axiRst   in sl := ' 0 '
axiReadMaster   in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiReadSlave   out AxiLiteReadSlaveType
axiWriteMaster   in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiWriteSlave   out AxiLiteWriteSlaveType
updatedResults   out sl
errorDet   out sl
busy   out sl
errMissedPacket   out sl
errLength   out sl
errDataBus   out sl
errEofe   out sl
errWordCnt   out slv ( 31 downto 0 )
errbitCnt   out slv ( 31 downto 0 )
packetRate   out slv ( 31 downto 0 )
packetLength   out slv ( 31 downto 0 )

Detailed Description

See also
entity

Definition at line 31 of file SsiPrbsRx.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 34 of file SsiPrbsRx.vhd.

◆ STATUS_CNT_WIDTH_G

STATUS_CNT_WIDTH_G natural range 1 to 32 := 32
Generic

Definition at line 35 of file SsiPrbsRx.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 36 of file SsiPrbsRx.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 38 of file SsiPrbsRx.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 39 of file SsiPrbsRx.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 40 of file SsiPrbsRx.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 41 of file SsiPrbsRx.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 42 of file SsiPrbsRx.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 43 of file SsiPrbsRx.vhd.

◆ CASCADE_SIZE_G

CASCADE_SIZE_G natural range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 44 of file SsiPrbsRx.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G natural range 4 to 48 := 9
Generic

Definition at line 45 of file SsiPrbsRx.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G natural range 1 to ( 2 ** 24 ) := 2 ** 8
Generic

Definition at line 46 of file SsiPrbsRx.vhd.

◆ PRBS_SEED_SIZE_G

PRBS_SEED_SIZE_G natural range 8 to 128 := 32
Generic

Definition at line 48 of file SsiPrbsRx.vhd.

◆ PRBS_TAPS_G

PRBS_TAPS_G NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
Generic

Definition at line 49 of file SsiPrbsRx.vhd.

◆ SLAVE_AXI_STREAM_CONFIG_G

SLAVE_AXI_STREAM_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
Generic

Definition at line 51 of file SsiPrbsRx.vhd.

◆ SLAVE_AXI_PIPE_STAGES_G

SLAVE_AXI_PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 52 of file SsiPrbsRx.vhd.

◆ MASTER_AXI_STREAM_CONFIG_G

MASTER_AXI_STREAM_CONFIG_G AxiStreamConfigType := ssiAxiStreamConfig ( 4 )
Generic

Definition at line 53 of file SsiPrbsRx.vhd.

◆ MASTER_AXI_PIPE_STAGES_G

MASTER_AXI_PIPE_STAGES_G natural range 0 to 16 := 0
Generic

Definition at line 54 of file SsiPrbsRx.vhd.

◆ sAxisClk

sAxisClk in sl
Port

Definition at line 57 of file SsiPrbsRx.vhd.

◆ sAxisRst

sAxisRst in sl := ' 0 '
Port

Definition at line 58 of file SsiPrbsRx.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 59 of file SsiPrbsRx.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 60 of file SsiPrbsRx.vhd.

◆ sAxisCtrl

sAxisCtrl out AxiStreamCtrlType
Port

Definition at line 61 of file SsiPrbsRx.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 63 of file SsiPrbsRx.vhd.

◆ mAxisRst

mAxisRst in sl := ' 0 '
Port

Definition at line 64 of file SsiPrbsRx.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 65 of file SsiPrbsRx.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
Port

Definition at line 66 of file SsiPrbsRx.vhd.

◆ axiClk

axiClk in sl := ' 0 '
Port

Definition at line 68 of file SsiPrbsRx.vhd.

◆ axiRst

axiRst in sl := ' 0 '
Port

Definition at line 69 of file SsiPrbsRx.vhd.

◆ axiReadMaster

axiReadMaster in AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
Port

Definition at line 70 of file SsiPrbsRx.vhd.

◆ axiReadSlave

axiReadSlave out AxiLiteReadSlaveType
Port

Definition at line 71 of file SsiPrbsRx.vhd.

◆ axiWriteMaster

axiWriteMaster in AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
Port

Definition at line 72 of file SsiPrbsRx.vhd.

◆ axiWriteSlave

axiWriteSlave out AxiLiteWriteSlaveType
Port

Definition at line 73 of file SsiPrbsRx.vhd.

◆ updatedResults

updatedResults out sl
Port

Definition at line 75 of file SsiPrbsRx.vhd.

◆ errorDet

errorDet out sl
Port

Definition at line 76 of file SsiPrbsRx.vhd.

◆ busy

busy out sl
Port

Definition at line 77 of file SsiPrbsRx.vhd.

◆ errMissedPacket

errMissedPacket out sl
Port

Definition at line 78 of file SsiPrbsRx.vhd.

◆ errLength

errLength out sl
Port

Definition at line 79 of file SsiPrbsRx.vhd.

◆ errDataBus

errDataBus out sl
Port

Definition at line 80 of file SsiPrbsRx.vhd.

◆ errEofe

errEofe out sl
Port

Definition at line 81 of file SsiPrbsRx.vhd.

◆ errWordCnt

errWordCnt out slv ( 31 downto 0 )
Port

Definition at line 82 of file SsiPrbsRx.vhd.

◆ errbitCnt

errbitCnt out slv ( 31 downto 0 )
Port

Definition at line 83 of file SsiPrbsRx.vhd.

◆ packetRate

packetRate out slv ( 31 downto 0 )
Port

Definition at line 84 of file SsiPrbsRx.vhd.

◆ packetLength

packetLength out slv ( 31 downto 0 )
Port

Definition at line 85 of file SsiPrbsRx.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file SsiPrbsRx.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 20 of file SsiPrbsRx.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 21 of file SsiPrbsRx.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file SsiPrbsRx.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 24 of file SsiPrbsRx.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 25 of file SsiPrbsRx.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 26 of file SsiPrbsRx.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 27 of file SsiPrbsRx.vhd.

The documentation for this class was generated from the following file: