SURF  1.0
SsiPrbsRateGen Entity Reference
+ Inheritance diagram for SsiPrbsRateGen:
+ Collaboration diagram for SsiPrbsRateGen:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_unsigned 
std_logic_arith 
StdRtlPkg  Package <StdRtlPkg>
AxiLitePkg  Package <AxiLitePkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>

Generics

TPD_G  time := 1 ns
AXI_ERROR_RESP_G  slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
VALID_THOLD_G  integer range 0 to ( 2 ** 24 ) := 1
VALID_BURST_MODE_G  boolean := false
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
CASCADE_SIZE_G  natural range 1 to ( 2 ** 24 ) := 1
FIFO_ADDR_WIDTH_G  natural range 4 to 48 := 9
AXIS_CLK_FREQ_G  real := 156 . 25E + 6
AXIS_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C

Ports

mAxisClk   in sl
mAxisRst   in sl
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
axilReadMaster   in AxiLiteReadMasterType
axilReadSlave   out AxiLiteReadSlaveType
axilWriteMaster   in AxiLiteWriteMasterType
axilWriteSlave   out AxiLiteWriteSlaveType

Detailed Description

See also
entity

Definition at line 29 of file SsiPrbsRateGen.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 32 of file SsiPrbsRateGen.vhd.

◆ AXI_ERROR_RESP_G

AXI_ERROR_RESP_G slv ( 1 downto 0 ) := AXI_RESP_SLVERR_C
Generic

Definition at line 33 of file SsiPrbsRateGen.vhd.

◆ VALID_THOLD_G

VALID_THOLD_G integer range 0 to ( 2 ** 24 ) := 1
Generic

Definition at line 35 of file SsiPrbsRateGen.vhd.

◆ VALID_BURST_MODE_G

VALID_BURST_MODE_G boolean := false
Generic

Definition at line 36 of file SsiPrbsRateGen.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 37 of file SsiPrbsRateGen.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 38 of file SsiPrbsRateGen.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 39 of file SsiPrbsRateGen.vhd.

◆ CASCADE_SIZE_G

CASCADE_SIZE_G natural range 1 to ( 2 ** 24 ) := 1
Generic

Definition at line 40 of file SsiPrbsRateGen.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G natural range 4 to 48 := 9
Generic

Definition at line 41 of file SsiPrbsRateGen.vhd.

◆ AXIS_CLK_FREQ_G

AXIS_CLK_FREQ_G real := 156 . 25E + 6
Generic

Definition at line 43 of file SsiPrbsRateGen.vhd.

◆ AXIS_CONFIG_G

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 47 of file SsiPrbsRateGen.vhd.

◆ mAxisRst

mAxisRst in sl
Port

Definition at line 48 of file SsiPrbsRateGen.vhd.

◆ mAxisMaster

Definition at line 49 of file SsiPrbsRateGen.vhd.

◆ mAxisSlave

Definition at line 50 of file SsiPrbsRateGen.vhd.

◆ axilReadMaster

Definition at line 51 of file SsiPrbsRateGen.vhd.

◆ axilReadSlave

Definition at line 52 of file SsiPrbsRateGen.vhd.

◆ axilWriteMaster

Definition at line 53 of file SsiPrbsRateGen.vhd.

◆ axilWriteSlave

Definition at line 54 of file SsiPrbsRateGen.vhd.

◆ ieee

ieee
Library

Definition at line 17 of file SsiPrbsRateGen.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 18 of file SsiPrbsRateGen.vhd.

◆ std_logic_unsigned

Definition at line 19 of file SsiPrbsRateGen.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 20 of file SsiPrbsRateGen.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 22 of file SsiPrbsRateGen.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 23 of file SsiPrbsRateGen.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 24 of file SsiPrbsRateGen.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 25 of file SsiPrbsRateGen.vhd.


The documentation for this class was generated from the following file: