SURF  1.0
Generics | Ports | Libraries | Use Clauses
SsiAxiLiteMaster Entity Reference
protocols » ssi
+ Inheritance diagram for SsiAxiLiteMaster:
+ Collaboration diagram for SsiAxiLiteMaster:

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>
SsiPkg  Package <SsiPkg>
AxiLitePkg  Package <AxiLitePkg>

Generics

TPD_G  time := 1 ns
RESP_THOLD_G  integer range 0 to ( 2 ** 24 ) := 1
SLAVE_READY_EN_G  boolean := false
EN_32BIT_ADDR_G  boolean := false
BRAM_EN_G  boolean := true
XIL_DEVICE_G  string := " 7SERIES "
USE_BUILT_IN_G  boolean := false
ALTERA_SYN_G  boolean := false
ALTERA_RAM_G  string := " M9K "
GEN_SYNC_FIFO_G  boolean := false
FIFO_ADDR_WIDTH_G  integer range 4 to 48 := 9
FIFO_PAUSE_THRESH_G  integer range 1 to ( 2 ** 24 ) := 2 ** 8
AXI_STREAM_CONFIG_G  AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C

Ports

sAxisClk   in sl
sAxisRst   in sl := ' 0 '
sAxisMaster   in AxiStreamMasterType
sAxisSlave   out AxiStreamSlaveType
sAxisCtrl   out AxiStreamCtrlType
mAxisClk   in sl
mAxisRst   in sl := ' 0 '
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType
axiLiteClk   in sl
axiLiteRst   in sl
mAxiLiteWriteMaster   out AxiLiteWriteMasterType
mAxiLiteWriteSlave   in AxiLiteWriteSlaveType
mAxiLiteReadMaster   out AxiLiteReadMasterType
mAxiLiteReadSlave   in AxiLiteReadSlaveType

Detailed Description

See also
entity

Definition at line 61 of file SsiAxiLiteMaster.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 64 of file SsiAxiLiteMaster.vhd.

◆ RESP_THOLD_G

RESP_THOLD_G integer range 0 to ( 2 ** 24 ) := 1
Generic

Definition at line 67 of file SsiAxiLiteMaster.vhd.

◆ SLAVE_READY_EN_G

SLAVE_READY_EN_G boolean := false
Generic

Definition at line 68 of file SsiAxiLiteMaster.vhd.

◆ EN_32BIT_ADDR_G

EN_32BIT_ADDR_G boolean := false
Generic

Definition at line 69 of file SsiAxiLiteMaster.vhd.

◆ BRAM_EN_G

BRAM_EN_G boolean := true
Generic

Definition at line 70 of file SsiAxiLiteMaster.vhd.

◆ XIL_DEVICE_G

XIL_DEVICE_G string := " 7SERIES "
Generic

Definition at line 71 of file SsiAxiLiteMaster.vhd.

◆ USE_BUILT_IN_G

USE_BUILT_IN_G boolean := false
Generic

Definition at line 72 of file SsiAxiLiteMaster.vhd.

◆ ALTERA_SYN_G

ALTERA_SYN_G boolean := false
Generic

Definition at line 73 of file SsiAxiLiteMaster.vhd.

◆ ALTERA_RAM_G

ALTERA_RAM_G string := " M9K "
Generic

Definition at line 74 of file SsiAxiLiteMaster.vhd.

◆ GEN_SYNC_FIFO_G

GEN_SYNC_FIFO_G boolean := false
Generic

Definition at line 75 of file SsiAxiLiteMaster.vhd.

◆ FIFO_ADDR_WIDTH_G

FIFO_ADDR_WIDTH_G integer range 4 to 48 := 9
Generic

Definition at line 76 of file SsiAxiLiteMaster.vhd.

◆ FIFO_PAUSE_THRESH_G

FIFO_PAUSE_THRESH_G integer range 1 to ( 2 ** 24 ) := 2 ** 8
Generic

Definition at line 77 of file SsiAxiLiteMaster.vhd.

◆ AXI_STREAM_CONFIG_G

AXI_STREAM_CONFIG_G AxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
Generic

Definition at line 80 of file SsiAxiLiteMaster.vhd.

◆ sAxisClk

sAxisClk in sl
Port

Definition at line 84 of file SsiAxiLiteMaster.vhd.

◆ sAxisRst

sAxisRst in sl := ' 0 '
Port

Definition at line 85 of file SsiAxiLiteMaster.vhd.

◆ sAxisMaster

sAxisMaster in AxiStreamMasterType
Port

Definition at line 86 of file SsiAxiLiteMaster.vhd.

◆ sAxisSlave

sAxisSlave out AxiStreamSlaveType
Port

Definition at line 87 of file SsiAxiLiteMaster.vhd.

◆ sAxisCtrl

sAxisCtrl out AxiStreamCtrlType
Port

Definition at line 88 of file SsiAxiLiteMaster.vhd.

◆ mAxisClk

mAxisClk in sl
Port

Definition at line 91 of file SsiAxiLiteMaster.vhd.

◆ mAxisRst

mAxisRst in sl := ' 0 '
Port

Definition at line 92 of file SsiAxiLiteMaster.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 93 of file SsiAxiLiteMaster.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 94 of file SsiAxiLiteMaster.vhd.

◆ axiLiteClk

axiLiteClk in sl
Port

Definition at line 97 of file SsiAxiLiteMaster.vhd.

◆ axiLiteRst

axiLiteRst in sl
Port

Definition at line 98 of file SsiAxiLiteMaster.vhd.

◆ mAxiLiteWriteMaster

mAxiLiteWriteMaster out AxiLiteWriteMasterType
Port

Definition at line 99 of file SsiAxiLiteMaster.vhd.

◆ mAxiLiteWriteSlave

mAxiLiteWriteSlave in AxiLiteWriteSlaveType
Port

Definition at line 100 of file SsiAxiLiteMaster.vhd.

◆ mAxiLiteReadMaster

mAxiLiteReadMaster out AxiLiteReadMasterType
Port

Definition at line 101 of file SsiAxiLiteMaster.vhd.

◆ mAxiLiteReadSlave

mAxiLiteReadSlave in AxiLiteReadSlaveType
Port

Definition at line 103 of file SsiAxiLiteMaster.vhd.

◆ ieee

ieee
Library

Definition at line 49 of file SsiAxiLiteMaster.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 50 of file SsiAxiLiteMaster.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 51 of file SsiAxiLiteMaster.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 52 of file SsiAxiLiteMaster.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 54 of file SsiAxiLiteMaster.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 55 of file SsiAxiLiteMaster.vhd.

◆ SsiPkg

SsiPkg
Package

Definition at line 56 of file SsiAxiLiteMaster.vhd.

◆ AxiLitePkg

AxiLitePkg
Package

Definition at line 57 of file SsiAxiLiteMaster.vhd.

The documentation for this class was generated from the following file: